?Verilog的QPSK調(diào)制實現(xiàn)

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QPSK調(diào)制一般采用兩種方式：（1）調(diào)相法? （2）四相位選擇法

一、調(diào)相法

?利用三段式狀態(tài)機，實現(xiàn)由輸入信號輸出 兩路正交相位調(diào)制輸出

`timescale 1ns / 1ps // // Company: // Engineer: // // Create Date: 2019/07/27 13:23:19 // Design Name: // Module Name: QPSK // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //module QPSK(clk,rst_n,din,valid_in,out_real,out_imag,valid_out);input clk;input rst_n;input valid_in; //控制信號輸入input din; //輸入信號output out_real; // 實部輸出output out_imag; //虛部輸出output valid_out; //已調(diào)制后信號輸出的標(biāo)志reg[15:0] out_real;reg[15:0] out_imag; reg valid_out;reg[1:0] temp;reg[1:0] state;reg[1:0] nextstate;parameter IDLE=2'b00,state1=2'b01,state2=2'b10,ONE=16'h0fff;always@(posedge clk) beginif(!rst_n)state <= IDLE;elsestate <= nextstate;endalways@(* )beginif(!rst_n)nextstate <= IDLE;elsebegincase(state) IDLE:beginif(valid_in == 1'b1)nextstate <= state1;else nextstate <= state; endstate1:begin if(valid_in == 1'b1) nextstate <= state2;else nextstate <= state; end state2:begin if(valid_in == 1'b1) nextstate <= state1;else nextstate <= state; end default:nextstate <= IDLE;endcaseendendalways@(posedge clk)beginif(!rst_n)temp <= 2'b00;elsebeginif(valid_in)temp <= {temp[0],din};elsetemp <= temp;endendalways@(posedge clk)beginif(!rst_n)beginout_real <= 16'b0000_0000_0000_0000;out_imag <= 16'b0000_0000_0000_0000;endelsebeginif(state==state2)case(temp)2'b00:beginout_real <= ONE;out_imag <= ONE;end2'b01:beginout_real <= ~ONE;out_imag <= ONE;end2'b11:beginout_real <= ~ONE;out_imag <= ~ONE;end2'b10:beginout_real <= ONE;out_imag <= ~ONE;enddefault:beginout_real <= 16'h0000;out_imag <= 16'h0000;endendcaseelsebeginout_real <= 16'b0000_0000_0000_0000;out_imag <= 16'b0000_0000_0000_0000;endendendalways@(posedge clk)beginif(!rst_n)beginvalid_out <= 1'b0;endelsebeginif(state==state2)valid_out <= 1'b1;elsebeginvalid_out <= 1'b0;endend end endmodule

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二、四相位選擇法

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module qpsk(clk,rst,x,y) input clk,rst; input x; //系統(tǒng)輸入信號:每4個∞1k周期輸入一個x的值 output y; /QPSK調(diào)制輸出信號:在8個ck周期內(nèi)按bit輸出reg [2: 0]count //計數(shù)器 reg [1: 0] xreg; //輸入信號的中間寄存器 reg [1: 0] yreg; reg[3:0] carriers;//4路載波信號/實現(xiàn)QPSκ解調(diào) assign y =(yreg == 2'b00)? carriers [3]: (yreg == 2'b01)? carriers [2]: (yreg == 2' b10)? carriers [1]: (yreg == 2 b11)? carriers [0] :0;//完成計數(shù)器,從而對模塊時鐘分頻 always @(posedge clk or negedge rst) if(!rst)count <= 3'b000; elsecount <= count +1 //寄存輸入:每4個c1k周期,將輸入x寄存到xreg中always @(posedge clk or negedge rst) if(!rst)xreg <= 2'b00; elseif(count[1:0]==2'b11)xreg <= {xreg[0],x};elsexreg <= xreg;//產(chǎn)生載波信號并且每8個周期將奇存器xeg的值送到y(tǒng)reg中,供后面判斷輸出 always @(posedge clk or negedge rst) if(!rst)begincarriers <= 4'b000;yreg <= 2'b00;end elsebegincase(count)3'b000:beginyreg <= xreg;carriers <= 4'b1100;end3'b010:carriers <= 4'b1001;3'b100:carriers <= 4'b0011;3'b110:carriers <= 4'b0110;default:carriers <= carriers;endcaseend endmodule

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參考資料：

1、基于Verilog HDL的通信系統(tǒng)設(shè)計? 陳曦

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