// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to
// suit user's needs .Comments are provided in each section to help the user
// fill out necessary details.
// *****************************************************************************
// Generated on "10/11/2020 23:13:57"// Verilog Test Bench template for design : test
//
// Simulation tool : ModelSim-Altera (Verilog)
// `timescale 1 ps/ 1 ps
module test_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg clr;
// wires
wire half_clk;// assign statements (if any)
test i1 (
// port map - connection between master ports and signals/registers .clk(clk),.clr(clr),.half_clk(half_clk)
);
initial
begin
clk = 0;
clr = 0;
#100;
clr = 1;
#2000;
$stop;
// code that executes only once
// insert code here --> begin // --> end
$display("Running testbench");
end
always
# 20 clk = ~clk;
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin always
@eachvec;
// --> end
end
endmodule
