将ADS1.2的工程迁移到KEIL上-基于2440
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将ADS1.2的工程迁移到KEIL上-基于2440
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新版的MDK支持2440相關芯片,但是很多人的工程都是基于ADS1.2開發,文字不好看,兼容性不好等等問題,而且電腦上裝太多開發工具切換起來也麻煩,所以切換到MDK開發2440裸機程序應該是一個很好的選擇
1.???????新建MDK工程,芯片選擇2440
不拷貝啟動代碼,因為我們用自己的啟動代碼
2.???????建立工程目錄分級,建立完成后如下所示
拷貝相應代碼到對應目錄中
Option中拷貝
Core中拷貝
建立新的main文件
將文件加入工程
路徑中建立包含
還要為asm文件建立包含
修改2440init.s文件
首先,MDK默認放在最前面的段是RESET段,將2440init.s第84行(可能你的不是) AREA??? Init,CODE,READONLY修改為 AREA??? RESET,CODE,READONLY
這樣編譯器就能找到入口點了
在上面這句下面加上一行
PRESERVE8??? ;8 字對齊(為了讓匯編代碼8字節對齊)
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修改
IMPORT? |Image$$RO$$Base| ; Base of ROM code
IMPORT? |Image$$RO$$Limit|? ; End of ROM code (=start of ROM data)
IMPORT? |Image$$RW$$Base|?? ; Base of RAM to initialise
IMPORT? |Image$$ZI$$Base|?? ; Base and limit of area
IMPORT? |Image$$ZI$$Limit|? ; to zero initialise
這些是通過ADS的工程設置里面設定的RO Base和RW Base設定的,在MDK中的名稱不叫這個
修改為
IMPORT? |Image$$ER_ROM1$$RO$$Base|?? ; Base of ROM code
IMPORT? |Image$$ER_ROM1$$RO$$Limit|? ; End of ROM code (=start of ROM data)
IMPORT? |Image$$RW_RAM1$$RW$$Base|?? ; Base of RAM to initialise
IMPORT? |Image$$RW_RAM1$$ZI$$Base|?? ; Base and limit of area
IMPORT? |Image$$RW_RAM1$$ZI$$Limit|? ; to zero initialize
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上面的改了下面的這個也要改
BaseOfROM DCD |Image$$RO$$Base|
TopOfROM DCD |Image$$RO$$Limit|
BaseOfBSS DCD |Image$$RW$$Base|
BaseOfZero DCD |Image$$ZI$$Base|
EndOfBSS DCD |Image$$ZI$$Limit|
修改為
BaseOfROM? DCD? |Image$$ER_ROM1$$RO$$Base|
TopOfROM? DCD? |Image$$ER_ROM1$$RO$$Limit|
BaseOfBSS? DCD? |Image$$RW_RAM1$$RW$$Base|
BaseOfZero? DCD? |Image$$RW_RAM1$$ZI$$Base|
EndOfBSS? DCD? |Image$$RW_RAM1$$ZI$$Limit|
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此時還需要設置代碼運行區和存放區
ROM區域需要打開nand.c中的RdNF2SDRAM函數查看起始地址
我的起始地址為0x30000000 大小為0x100000
Size必須大于0x100000,RAM空間大于ROM空間且少于最大物理空間即可(不要忘了打鉤勾)
編寫Main函數,記住是首字母大寫
此時編譯就可以通過了
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隨意將一個ADS1.2編寫好的led驅動放進去,最終修改如下
Led.h
#ifndef __LED_H
#define __LED_H
#include "2440addr.h"typedef enum
{LED1 = 0, //GPB5LED2 = 1, //GPB6LED3 = 2, //GPB5LED4 = 3 //GPB8
}LEDn;void ledInit(LEDn led);
void ledInitAll(void);
void ledOn(LEDn led);
void ledOff(LEDn led);
void ledTurn(LEDn led);
unsigned char getLedStatus(LEDn led);//TQ2440led引腳 B5 B6 B7 B8#endif
Led.c
#include "led.h"void ledInit(LEDn led)
{if(led == LED1){rGPBCON &= ~(3<<10); //端口寫入01設置為輸出模式，先清零rGPBCON |= (1<<10); //設置為輸出rGPBUP &= ~(1<<5); //禁止上拉rGPBDAT |= (1<<5); //設置初始值為1，燈滅}else if(led == LED2){rGPBCON &= ~(3<<12);rGPBCON |= (1<<12);rGPBUP &= ~(1<<6);rGPBDAT |= (1<<6);}else if(led == LED3){rGPBCON &= ~(3<<14);rGPBCON |= (1<<14);rGPBUP &= ~(1<<7);rGPBDAT |= (1<<7);}else if(led == LED4){rGPBCON &= ~(3<<16);rGPBCON |= (1<<16);rGPBUP &= ~(1<<8);rGPBDAT |= (1<<8);}
}void ledInitAll(void)
{rGPBCON &=~((3<<10)|(3<<12)|(3<<14)|(3<<16)); //對GPBCON[10:17]清零rGPBCON |=((1<<10)|(1<<12)|(1<<14)|(1<<16)); //設置GPB5~8為輸出rGPBUP &=~((1<<5)|(1<<6)|(1<<7)|(1<<8)); //設置GPB5~8的上拉功能rGPBDAT |=(1<<5)|(1<<6)|(1<<7)|(1<<8); //關閉LED
}void ledOn(LEDn led)
{rGPBDAT &= ~(1<<(5+led));
}void ledOff(LEDn led)
{rGPBDAT |= (1<<(5+led));
}void ledTurn(LEDn led)
{if(getLedStatus(led))ledOn(led);else ledOff(led);
}unsigned char getLedStatus(LEDn led)//獲取led狀態，滅為1亮為0
{if((rGPBDAT & (1<<(5+led))))return 1;else return 0;
}
Main.c
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#include "2440addr.h"
#include "led.h"
void Delay(void)
{int i;for(i=0;i<1000000;i++);
}int Main()
{ledInitAll();while(1){ledTurn(LED1);Delay();ledTurn(LED2);Delay();ledTurn(LED3);Delay();ledTurn(LED4);Delay();}
}最后編譯,結果如下
但是生成的是HEX,我們需要指令轉換成BIN文件
在這里寫入指令
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記住對勾!
編譯,提示如下
BIN文件生成OK了
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下載進去,流水燈完全正常,收工!
最后附帶修改好了2440init.s文件
2440init.s
;=========================================
; NAME: 2440INIT.S
; DESC: C start up codes
; Configure memory, ISR ,stacks
; Initialize C-variables
;=========================================GET option.incGET memcfg.incGET 2440addr.incBIT_SELFREFRESH EQU (1<<22);Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0;The location of stacks
UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.GBLL THUMBCODE[ {CONFIG} = 16
THUMBCODE SETL {TRUE}CODE32|
THUMBCODE SETL {FALSE}]MACROMOV_PC_LR[ THUMBCODEbx lr|mov pc,lr]MENDMACROMOVEQ_PC_LR[ THUMBCODEbxeq lr|moveq pc,lr]MENDMACRO
$HandlerLabel HANDLER $HandleLabel$HandlerLabelsub sp,sp,#4 ;decrement sp(to store jump address)stmfd sp!,{r0} ;PUSH the work register to stack(lr does not push because it return to original address)ldr r0,=$HandleLabel;load the address of HandleXXX to r0ldr r0,[r0] ;load the contents(service routine start address) of HandleXXXstr r0,[sp,#4] ;store the contents(ISR) of HandleXXX to stackldmfd sp!,{r0,pc} ;POP the work register and pc(jump to ISR)MENDIMPORT |Image$$ER_ROM1$$RO$$Base| ; Base of ROM code IMPORT |Image$$ER_ROM1$$RO$$Limit| ; End of ROM code (=start of ROM data) IMPORT |Image$$RW_RAM1$$RW$$Base| ; Base of RAM to initialise IMPORT |Image$$RW_RAM1$$ZI$$Base| ; Base and limit of area IMPORT |Image$$RW_RAM1$$ZI$$Limit| ; to zero initialise IMPORT MMU_SetAsyncBusModeIMPORT MMU_SetFastBusMode ;IMPORT Main ; The main entry of mon programIMPORT RdNF2SDRAM ; Copy Image from Nand Flash to SDRAMAREA RESET,CODE,READONLYPRESERVE8 ;8 字對齊 ENTRYEXPORT __ENTRY
__ENTRY
ResetEntry;1)The code, which converts to Big-endian, should be in little endian code.;2)The following little endian code will be compiled in Big-Endian mode.; The code byte order should be changed as the memory bus width.;3)The pseudo instruction,DCD can not be used here because the linker generates error.ASSERT :DEF:ENDIAN_CHANGE[ ENDIAN_CHANGEASSERT :DEF:ENTRY_BUS_WIDTH[ ENTRY_BUS_WIDTH=32b ChangeBigEndian ;DCD 0xea000007][ ENTRY_BUS_WIDTH=16andeq r14,r7,r0,lsl #20 ;DCD 0x0007ea00][ ENTRY_BUS_WIDTH=8streq r0,[r0,-r10,ror #1] ;DCD 0x070000ea]|b ResetHandler]b HandlerUndef ;handler for Undefined modeb HandlerSWI ;handler for SWI interruptb HandlerPabort ;handler for PAbortb HandlerDabort ;handler for DAbortb . ;reservedb HandlerIRQ ;handler for IRQ interruptb HandlerFIQ ;handler for FIQ interrupt;@0x20b EnterPWDN ; Must be @0x20.
ChangeBigEndian
;@0x24[ ENTRY_BUS_WIDTH=32DCD 0xee110f10 ;0xee110f10 => mrc p15,0,r0,c1,c0,0DCD 0xe3800080 ;0xe3800080 => orr r0,r0,#0x80; //Big-endianDCD 0xee010f10 ;0xee010f10 => mcr p15,0,r0,c1,c0,0][ ENTRY_BUS_WIDTH=16DCD 0x0f10ee11DCD 0x0080e380DCD 0x0f10ee01][ ENTRY_BUS_WIDTH=8DCD 0x100f11eeDCD 0x800080e3DCD 0x100f01ee]DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode.DCD 0xffffffffDCD 0xffffffffDCD 0xffffffffDCD 0xffffffffb ResetHandlerHandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabortIsrIRQsub sp,sp,#4 ;reserved for PCstmfd sp!,{r8-r9}ldr r9,=INTOFFSETldr r9,[r9]ldr r8,=HandleEINT0add r8,r8,r9,lsl #2ldr r8,[r8]str r8,[sp,#8]ldmfd sp!,{r8-r9,pc}LTORG;=======
; ENTRY
;=======
ResetHandlerldr r0,=WTCON ;watch dog disableldr r1,=0x0str r1,[r0]ldr r0,=INTMSKldr r1,=0xffffffff ;all interrupt disablestr r1,[r0]ldr r0,=INTSUBMSKldr r1,=0x7fff ;all sub interrupt disablestr r1,[r0][ {FALSE}; GPBDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);; Led_Displayldr r0,=GPBCONldr r1,=0x00555555str r1,[r0]ldr r0,=GPBDATldr r1,=0x07festr r1,[r0]];To reduce PLL lock time, adjust the LOCKTIME register.ldr r0,=LOCKTIMEldr r1,=0xffffffstr r1,[r0][ PLL_ON_START; Added for confirm clock divide. for 2440.; Setting value Fclk:Hclk:Pclkldr r0,=CLKDIVNldr r1,=CLKDIV_VAL ; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.str r1,[r0];program has not been copied, so use these directly[ CLKDIV_VAL>1 ; means Fclk:Hclk is not 1:1.mrc p15,0,r0,c1,c0,0orr r0,r0,#0xc0000000;R1_nF:OR:R1_iAmcr p15,0,r0,c1,c0,0|mrc p15,0,r0,c1,c0,0bic r0,r0,#0xc0000000;R1_iA:OR:R1_nFmcr p15,0,r0,c1,c0,0];Configure UPLLldr r0,=UPLLCONldr r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV) ;Fin = 12.0MHz, UCLK = 48MHzstr r1,[r0]nop ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.nopnopnopnopnopnop;Configure MPLLldr r0,=MPLLCONldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) ;Fin = 12.0MHz, FCLK = 400MHzstr r1,[r0]];Check if the boot is caused by the wake-up from SLEEP mode.ldr r1,=GSTATUS2ldr r0,[r1]tst r0,#0x2;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.bne WAKEUP_SLEEPEXPORT StartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp;Set memory control registersadrl r0,SMRDATAldr r1,=BWSCON ;BWSCON Addressadd r2, r0, #52 ;End address of SMRDATA0ldr r3, [r0], #4str r3, [r1], #4cmp r2, r0bne %B0;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;; When EINT0 is pressed, Clear SDRAM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; check if EIN0 button is pressedldr r0,=GPFCONldr r1,=0x0str r1,[r0]ldr r0,=GPFUPldr r1,=0xffstr r1,[r0]ldr r1,=GPFDATldr r0,[r1]bic r0,r0,#(0x1e<<1) ; bit cleartst r0,#0x1bne %F1; Clear SDRAM Startldr r0,=GPFCONldr r1,=0x55aastr r1,[r0]ldr r0,=GPFDATldr r1,=0x0str r1,[r0] ;LED=****mov r1,#0mov r2,#0mov r3,#0mov r4,#0mov r5,#0mov r6,#0mov r7,#0mov r8,#0ldr r9,=0x4000000 ;64MBldr r0,=0x30000000
0 stmia r0!,{r1-r8}subs r9,r9,#32 bne %B0;Clear SDRAM End1;Initialize stacksbl InitStacks;===========================================================ldr r0, =BWSCONldr r0, [r0]ands r0, r0, #6 ;OM[1:0] != 0, NOR FLash bootbne copy_proc_beg ;do not read nand flashadr r0, ResetEntry ;OM[1:0] == 0, NAND FLash bootcmp r0, #0 ;if use Multi-ice, bne copy_proc_beg ;do not read nand flash for boot;nop
;===========================================================
nand_boot_beg[ {TRUE}bl RdNF2SDRAM]ldr pc, =copy_proc_beg
;===========================================================
copy_proc_begadr r0, ResetEntryldr r2, BaseOfROMcmp r0, r2ldreq r0, TopOfROMbeq InitRam ldr r3, TopOfROM
0 ldmia r0!, {r4-r7}stmia r2!, {r4-r7}cmp r2, r3bcc %B0sub r2, r2, r3sub r0, r0, r2 InitRam ldr r2, BaseOfBSSldr r3, BaseOfZero
0cmp r2, r3ldrcc r1, [r0], #4strcc r1, [r2], #4bcc %B0 mov r0, #0ldr r3, EndOfBSS
1 cmp r2, r3strcc r0, [r2], #4bcc %B1ldr pc, =%F2 ;goto compiler address
2; [ CLKDIV_VAL>1 ; means Fclk:Hclk is not 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ];===========================================================; Setup IRQ handlerldr r0,=HandleIRQ ;This routine is neededldr r1,=IsrIRQ ;if there is not 'subs pc,lr,#4' at 0x18, 0x1cstr r1,[r0][ :LNOT:THUMBCODEbl Main ;Do not use main() because ......b .][ THUMBCODE ;for start-up code for Thumb modeorr lr,pc,#1bx lrCODE16bl Main ;Do not use main() because ......b .CODE32];function initializing stacks
InitStacks;Do not use DRAM,such as stmfd,ldmfd......;SVCstack is initialized before;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'mrs r0,cpsrbic r0,r0,#MODEMASKorr r1,r0,#UNDEFMODE:OR:NOINTmsr cpsr_cxsf,r1 ;UndefModeldr sp,=UndefStack ; UndefStack=0x33FF_5C00orr r1,r0,#ABORTMODE:OR:NOINTmsr cpsr_cxsf,r1 ;AbortModeldr sp,=AbortStack ; AbortStack=0x33FF_6000orr r1,r0,#IRQMODE:OR:NOINTmsr cpsr_cxsf,r1 ;IRQModeldr sp,=IRQStack ; IRQStack=0x33FF_7000orr r1,r0,#FIQMODE:OR:NOINTmsr cpsr_cxsf,r1 ;FIQModeldr sp,=FIQStack ; FIQStack=0x33FF_8000bic r0,r0,#MODEMASK:OR:NOINTorr r1,r0,#SVCMODEmsr cpsr_cxsf,r1 ;SVCModeldr sp,=SVCStack ; SVCStack=0x33FF_5800;USER mode has not be initialized.mov pc,lr;The LR register will not be valid if the current mode is not SVC mode.LTORGSMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+(Tchr<<16)+REFCNT)DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128MDCD 0x30 ;MRSR6 CL=3clkDCD 0x30 ;MRSR7 CL=3clkBaseOfROM DCD |Image$$ER_ROM1$$RO$$Base|
TopOfROM DCD |Image$$ER_ROM1$$RO$$Limit|
BaseOfBSS DCD |Image$$RW_RAM1$$RW$$Base|
BaseOfZero DCD |Image$$RW_RAM1$$ZI$$Base|
EndOfBSS DCD |Image$$RW_RAM1$$ZI$$Limit| ALIGN;Function for entering power down mode
; 1. SDRAM should be in self-refresh mode.
; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
; 4. The I-cache may have to be turned on.
; 5. The location of the following code may have not to be changed.;void EnterPWDN(int CLKCON);
EnterPWDNmov r2,r0 ;r2=rCLKCONtst r0,#0x8 ;SLEEP mode?bne ENTER_SLEEPENTER_STOPldr r0,=REFRESHldr r3,[r0] ;r3=rREFRESHmov r1, r3orr r1, r1, #BIT_SELFREFRESHstr r1, [r0] ;Enable SDRAM self-refreshmov r1,#16 ;wait until self-refresh is issued. may not be needed.
0 subs r1,r1,#1bne %B0ldr r0,=CLKCON ;enter STOP mode.str r2,[r0]mov r1,#32
0 subs r1,r1,#1 ;1) wait until the STOP mode is in effect.bne %B0 ;2) Or wait here until the CPU&Peripherals will be turned-off; Entering SLEEP mode, only the reset by wake-up is available.ldr r0,=REFRESH ;exit from SDRAM self refresh mode.str r3,[r0]MOV_PC_LRENTER_SLEEP;NOTE.;1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.ldr r0,=REFRESHldr r1,[r0] ;r1=rREFRESHorr r1, r1, #BIT_SELFREFRESHstr r1, [r0] ;Enable SDRAM self-refreshmov r1,#16 ;Wait until self-refresh is issued,which may not be needed.
0 subs r1,r1,#1bne %B0ldr r1,=MISCCRldr r0,[r1]orr r0,r0,#(7<<17) ;Set SCLK0=0, SCLK1=0, SCKE=0.str r0,[r1]ldr r0,=CLKCON ; Enter sleep modestr r2,[r0]b . ;CPU will die here.WAKEUP_SLEEP;Release SCLKn after wake-up from the SLEEP mode.ldr r1,=MISCCRldr r0,[r1]bic r0,r0,#(7<<17) ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.str r0,[r1];Set memory control registersldr r0,=SMRDATAldr r1,=BWSCON ;BWSCON Addressadd r2, r0, #52 ;End address of SMRDATA
0ldr r3, [r0], #4str r3, [r1], #4cmp r2, r0bne %B0mov r1,#256
0 subs r1,r1,#1 ;1) wait until the SelfRefresh is released.bne %B0ldr r1,=GSTATUS3 ;GSTATUS3 has the start address just after SLEEP wake-upldr r0,[r1]mov pc,r0;=====================================================================
; Clock division test
; Assemble code, because VSYNC time is very short
;=====================================================================EXPORT CLKDIV124EXPORT CLKDIV144CLKDIV124ldr r0, = CLKDIVNldr r1, = 0x3 ; 0x3 = 1:2:4str r1, [r0]
; wait until clock is stablenopnopnopnopnopldr r0, = REFRESHldr r1, [r0]bic r1, r1, #0xffbic r1, r1, #(0x7<<8)orr r1, r1, #0x470 ; REFCNT135str r1, [r0]nopnopnopnopnopmov pc, lrCLKDIV144ldr r0, = CLKDIVNldr r1, = 0x4 ; 0x4 = 1:4:4str r1, [r0]
; wait until clock is stablenopnopnopnopnopldr r0, = REFRESHldr r1, [r0]bic r1, r1, #0xffbic r1, r1, #(0x7<<8)orr r1, r1, #0x630 ; REFCNT675 - 1520str r1, [r0]nopnopnopnopnopmov pc, lrALIGNAREA RamData, DATA, READWRITE^ _ISR_STARTADDRESS ; _ISR_STARTADDRESS=0x33FF_FF00
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4;Do not use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
;@0x33FF_FF20
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4_7 # 4
HandleEINT8_23 # 4
HandleCAM # 4 ; Added for 2440.
HandleBATFLT # 4
HandleTICK # 4
HandleWDT # 4
HandleTIMER0 # 4
HandleTIMER1 # 4
HandleTIMER2 # 4
HandleTIMER3 # 4
HandleTIMER4 # 4
HandleUART2 # 4
;@0x33FF_FF60
HandleLCD # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleDMA2 # 4
HandleDMA3 # 4
HandleMMC # 4
HandleSPI0 # 4
HandleUART1 # 4
HandleNFCON # 4 ; Added for 2440.
HandleUSBD # 4
HandleUSBH # 4
HandleIIC # 4
HandleUART0 # 4
HandleSPI1 # 4
HandleRTC # 4
HandleADC # 4
;@0x33FF_FFA0END
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轉載于:https://www.cnblogs.com/dengxiaojun/p/4279425.html
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