功能：

基于Nexys4DDR開發(fā)板實(shí)現(xiàn)的數(shù)字鐘，六位數(shù)碼管顯示時(shí)分秒，可切換24時(shí)制/12時(shí)制，有整點(diǎn)報(bào)時(shí)功能（led燈閃爍）。

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Verilog代碼：

`timescale 1ns / 1ps//數(shù)字鐘，輸入100M時(shí)鐘信號(hào)，控制數(shù)字顯示器通過高頻掃描來顯示當(dāng)前時(shí)間 module digital_clock(clk_100M, select, y, h, min, sh, led1, led2);input clk_100M;input h, min, sh;output led1, led2;output[7:0] y;output[7:0] select;reg led1;wire led2;reg[16:0] count;reg[7:0] select, y;wire clk_1hz, clk_1khz, clk_100M;wire[3:0] s0, s1, m0, m1, h0, h1;//變量說明：//clk_100M是100M的時(shí)鐘信號(hào)select是控制數(shù)碼管亮暗的使能端，y是七段譯碼器的輸出端//led2是正點(diǎn)報(bào)時(shí)燈//count用于記錄時(shí)鐘走過的秒數(shù)，clk_1hz是分頻后1hz的時(shí)鐘信號(hào)//s0~h1記錄秒、分、時(shí)的個(gè)十位//h、min分別為分鐘和小時(shí)校時(shí),sh==0時(shí)為24時(shí)制，sh==1時(shí)為12時(shí)制,led1是上下午指示燈//分頻器獲得1hz和1khz時(shí)鐘信號(hào)，輸入輸出必須為wire型frequency_divider fred(clk_1hz, clk_1khz, clk_100M);//計(jì)時(shí)模塊,每24*60*60秒為一輪initial count = 0;always@(posedge clk_1hz)begincase({h,min})2'b01: if(sh==0 && count < 17'd86341) count <= count + 6'd60;//24小時(shí)制的分鐘校時(shí)else if(sh==1 && count < 16'd43141) count <= count + 6'd60;//12小時(shí)制的分鐘校時(shí)else count <= 0;2'b10: if(sh==0 && count < 17'd82800) count <= count + 12'd3600;//24小時(shí)制的小時(shí)校時(shí)else if(sh==0 && count >= 17'd82800) count <= 0;//24小時(shí)制清零else if(sh==1 && count < 16'd43200) count <= count + 12'd3600;//12小時(shí)制的小時(shí)校時(shí)else count <= 12'd3600;//12小時(shí)制清零2'b00:if(sh==0 && count < 17'd86399) count <= count + 1;else if(sh==0 && count >= 17'd86399) count <= 0;else if(sh==1 && count < 16'd46799) count <= count + 1;else count <= 3600;2'b11: count <= count;endcaseend//獲得當(dāng)前時(shí)間的時(shí)分秒各位數(shù)time_count t(count, s0, s1, m0, m1, h0, h1);//12小時(shí)制的上下午指示燈，上午滅，下午亮initial led1 = 0;always@(h1) if(sh==1 && {h1,h0}==1) led1 <= ~led1;always@(posedge sh)if(count > 16'd43200)begincount <= count - 16'd43200;led1 <= ~led1;end//正點(diǎn)報(bào)時(shí)showtime show(clk_1hz, count, led2);//獲取當(dāng)前時(shí)間的時(shí)分秒各位數(shù)的七段譯碼值wire[7:0] y0, y1, y2, y3, y4, y5;decoder4_8 d1(s0, y0);decoder4_8 d2(s1, y1);decoder4_8 d3(m0, y2);decoder4_8 d4(m1, y3);decoder4_8 d5(h0, y4);decoder4_8 d6(h1, y5);//數(shù)碼管高頻顯示當(dāng)前小時(shí)、分鐘和秒reg[2:0] flag;//flag相當(dāng)于模6計(jì)數(shù)器，對(duì)應(yīng)時(shí)分秒的六位數(shù)initialbegin flag = 0;y = 0;select = 0;endalways@(posedge clk_1khz) flag = (flag+1)%6;always@(flag)beginif(flag == 3'd0)//顯示秒的個(gè)位beginselect <= 8'b1111_1110;y <= y0;endif(flag == 3'd1)//顯示秒的十位beginselect <= 8'b1111_1101;y <= y1;endif(flag == 3'd2)//顯示分鐘的個(gè)位beginselect <= 8'b1111_1011;y <= y2;endif(flag == 3'd3)//顯示分鐘的十位beginselect <= 8'b1111_0111;y <= y3;endif(flag == 3'd4)//顯示小時(shí)的個(gè)位beginselect <= 8'b1110_1111;y <= y4;endif(flag == 3'd5)//顯示小時(shí)的十位beginselect <= 8'b1101_1111;y <= y5;endend endmodule//分頻器 module frequency_divider(clk_1hz, clk_1khz, clk_100M);input clk_100M;output clk_1hz, clk_1khz;reg[16:0] count1;reg[9:0] count2;reg clk_1khz, clk_1hz;//變量說明：//輸入clk_100M為100M的時(shí)鐘信號(hào)//count1和count2是分頻器計(jì)的數(shù)變量，clk_1khz和clk_1hz是分頻器的輸出//中間變量必須在源程序中初始化！！！initial begincount1 = 0;count2 = 0;clk_1khz = 0;clk_1hz = 0;end//100M 100000分頻得到1khzalways@(posedge clk_100M)beginif(count1 == 17'd49999)beginclk_1khz <= ~clk_1khz;count1 <= 0;endelse count1 <= count1 + 1;end//1khz 1000分頻得到1hzalways@(posedge clk_1khz)beginif(count2 == 10'd499)beginclk_1hz <= ~clk_1hz;count2 <= 0;endelse count2 <= count2 + 1;end endmodule //七段譯碼器 module decoder4_8(x, y);input[3:0] x;output[7:0] y;reg[7:0] y;always@(x)case(x)4'd0: y <= 8'h03;//數(shù)碼管顯示04'd1: y <= 8'h9f;//數(shù)碼管顯示14'd2: y <= 8'h25;//數(shù)碼管顯示24'd3: y <= 8'h0d;//數(shù)碼管顯示34'd4: y <= 8'h99;//數(shù)碼管顯示44'd5: y <= 8'h49;//數(shù)碼管顯示54'd6: y <= 8'h41;//數(shù)碼管顯示64'd7: y <= 8'h1f;//數(shù)碼管顯示74'd8: y <= 8'h01;//數(shù)碼管顯示84'd9: y <= 8'h09;//數(shù)碼管顯示9endcase endmodule //時(shí)分秒計(jì)算器 module time_count(count, s0, s1, m0, m1, h0, h1);input[16:0] count;output[3:0] s0, s1, m0, m1, h0, h1;reg[3:0] s0, s1, m0, m1, h0, h1;//分別對(duì)應(yīng)秒、分、時(shí)的個(gè)位、十位initial begins0 = 0; s1 = 0; m0 = 0; m1 = 0; h0 = 0; h1 = 0;endalways@(count)begins0 <= (count%60)%10;//秒的個(gè)位s1 <= (count%60-((count%60)%10))/10;//秒的十位m0 <= (((count-count%60)/60)%60)%10;//分鐘的個(gè)位m1 <= ((((count-count%60)/60)-((count-count%60)/60)%10)%60)/10;//分鐘的十位h0 <= ((count-count%3600)/3600)%10;//小時(shí)的個(gè)位h1 <= (((count-count%3600)/3600)-((count-count%3600)/3600)%10)/10;//小時(shí)的十位end endmodule //正點(diǎn)報(bào)時(shí),幾點(diǎn)就亮幾下 module showtime(clk_1hz, count, led2);input clk_1hz;input[16:0] count;output led2;reg led2;reg[4:0] clock_number;initial begin clock_number = 0; led2 = 0; endalways@(clk_1hz)beginif(clock_number == 0)case(count)17'd3598: clock_number <= 2;//馬上1點(diǎn)17'd7197: clock_number <= 4;//馬上2點(diǎn)17'd10796: clock_number <= 6;//馬上3點(diǎn)17'd14395: clock_number <= 8;//馬上4點(diǎn)17'd17994: clock_number <= 10;//馬上5點(diǎn)17'd21592: clock_number <= 12;//馬上6點(diǎn)17'd25192: clock_number <= 14;//馬上7點(diǎn)17'd28791: clock_number <= 16;//馬上8點(diǎn)17'd32390: clock_number <= 18;//馬上9點(diǎn)17'd35989: clock_number <= 20;//馬上10點(diǎn)17'd39588: clock_number <= 22;//馬上11點(diǎn)17'd43187: clock_number <= 24;//馬上12點(diǎn)17'd46786: clock_number <= 26;//馬上13點(diǎn)17'd50385: clock_number <= 28;//馬上14點(diǎn)17'd53984: clock_number <= 30;//馬上15點(diǎn)17'd57583: clock_number <= 32;//馬上16點(diǎn)17'd61182: clock_number <= 34;//馬上17點(diǎn)endcase elsebeginled2 <= ~led2;clock_number <= clock_number - 1;endend endmodule

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管腳約束文件.ucf

NET "y<7>" LOC=T10 | IOSTANDARD=LVCMOS33; #IO_L24N_T3_A00_D16_14 NET "y<6>" LOC=R10 | IOSTANDARD=LVCMOS33; #IO_25_14 NET "y<5>" LOC=K16 | IOSTANDARD=LVCMOS33; #IO_25_15 NET "y<4>" LOC=K13 | IOSTANDARD=LVCMOS33; #IO_L17P_T2_A26_15 NET "y<3>" LOC=P15 | IOSTANDARD=LVCMOS33; #IO_L13P_T2_MRCC_14 NET "y<2>" LOC=T11 | IOSTANDARD=LVCMOS33; #IO_L19P_T3_A10_D26_14 NET "y<1>" LOC=L18 | IOSTANDARD=LVCMOS33; #IO_L4P_T0_D04_14 NET "y<0>" LOC=H15 | IOSTANDARD=LVCMOS33; #IO_L19N_T3_A21_VREF_15NET "select<0>" LOC=J17 | IOSTANDARD=LVCMOS33; #IO_L23P_T3_FOE_B_15 NET "select<1>" LOC=J18 | IOSTANDARD=LVCMOS33; #IO_L23N_T3_FWE_B_15 NET "select<2>" LOC=T9 | IOSTANDARD=LVCMOS33; #IO_L24P_T3_A01_D17_14 NET "select<3>" LOC=J14 | IOSTANDARD=LVCMOS33; #IO_L19P_T3_A22_15 NET "select<4>" LOC=P14 | IOSTANDARD=LVCMOS33; #IO_L8N_T1_D12_14 NET "select<5>" LOC=T14 | IOSTANDARD=LVCMOS33; #IO_L14P_T2_SRCC_14 NET "select<6>" LOC=K2 | IOSTANDARD=LVCMOS33; #IO_L23P_T3_35 NET "select<7>" LOC=U13 | IOSTANDARD=LVCMOS33; #IO_L23N_T3_A02_D18_14NET "clk_100M" LOC=E3 | IOSTANDARD=LVCMOS33; NET "min" LOC=J15 | IOSTANDARD=LVCMOS33; #IO_L24N_T3_RS0_15 NET "h" LOC=L16 | IOSTANDARD=LVCMOS33; #IO_L3N_T0_DQS_EMCCLK_14 NET "sh" LOC=M13 | IOSTANDARD=LVCMOS33; #IO_L13N_T2_MRCC_14 NET "sh" CLOCK_DEDICATED_ROUTE = FALSE;NET "led1" LOC=H17 | IOSTANDARD=LVCMOS33; #IO_L18P_T2_A24_15 NET "led2" LOC=K15 | IOSTANDARD=LVCMOS33; #IO_L24P_T3_RS1_15 《新程序員》：云原生和全面數(shù)字化實(shí)踐50位技術(shù)專家共同創(chuàng)作，文字、視頻、音頻交互閱讀

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