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目錄

• • armv8-aarch64
  • • 1、雙系統切換時寄存器的保存模型
    • 2、使用cpu_context結構體保存數據
    • • `gp_regs_t`結構體
      • `el3_state_t`結構體
      • `el1_sysregs_t`結構體

armv8-aarch64

1、雙系統切換時寄存器的保存模型

2、使用cpu_context結構體保存數據

以下是代碼片段

(trusted-firmware-a/include/lib/el3_runtime/aarch64/context.h)/** Top-level context structure which is used by EL3 firmware to* preserve the state of a core at EL1 in one of the two security* states and save enough EL3 meta data to be able to return to that* EL and security state. The context management library will be used* to ensure that SP_EL3 always points to an instance of this* structure at exception entry and exit. Each instance will* correspond to either the secure or the non-secure state.*/ typedef struct cpu_context {gp_regs_t gpregs_ctx;el3_state_t el3state_ctx;el1_sysregs_t el1_sysregs_ctx; #if CTX_INCLUDE_EL2_REGSel2_sysregs_t el2_sysregs_ctx; #endif #if CTX_INCLUDE_FPREGSfp_regs_t fpregs_ctx; #endifcve_2018_3639_t cve_2018_3639_ctx; #if CTX_INCLUDE_PAUTH_REGSpauth_t pauth_ctx; #endif } cpu_context_t;

gp_regs_t結構體

gp_regs_t結構體原型如下，其實就說一個數組uint64_t ctx_regs[num_regs];，該數組共有32個元素 ----即32個general purpose register: X0-X30,SP

#define DEFINE_REG_STRUCT(name, num_regs) \typedef struct name { \uint64_t ctx_regs[num_regs]; \} __aligned(16) name##_tDEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); #define CTX_GPREGS_OFFSET U(0x0) #define CTX_GPREG_X0 U(0x0) #define CTX_GPREG_X1 U(0x8) #define CTX_GPREG_X2 U(0x10) #define CTX_GPREG_X3 U(0x18) #define CTX_GPREG_X4 U(0x20) #define CTX_GPREG_X5 U(0x28) #define CTX_GPREG_X6 U(0x30) #define CTX_GPREG_X7 U(0x38) #define CTX_GPREG_X8 U(0x40) #define CTX_GPREG_X9 U(0x48) #define CTX_GPREG_X10 U(0x50) #define CTX_GPREG_X11 U(0x58) #define CTX_GPREG_X12 U(0x60) #define CTX_GPREG_X13 U(0x68) #define CTX_GPREG_X14 U(0x70) #define CTX_GPREG_X15 U(0x78) #define CTX_GPREG_X16 U(0x80) #define CTX_GPREG_X17 U(0x88) #define CTX_GPREG_X18 U(0x90) #define CTX_GPREG_X19 U(0x98) #define CTX_GPREG_X20 U(0xa0) #define CTX_GPREG_X21 U(0xa8) #define CTX_GPREG_X22 U(0xb0) #define CTX_GPREG_X23 U(0xb8) #define CTX_GPREG_X24 U(0xc0) #define CTX_GPREG_X25 U(0xc8) #define CTX_GPREG_X26 U(0xd0) #define CTX_GPREG_X27 U(0xd8) #define CTX_GPREG_X28 U(0xe0) #define CTX_GPREG_X29 U(0xe8) #define CTX_GPREG_LR U(0xf0) #define CTX_GPREG_SP_EL0 U(0xf8) #define CTX_GPREGS_END U(0x100)

el3_state_t結構體

el3_state_t結構體原型如下，其實就說一個數組uint64_t ctx_regs[num_regs];，該數組共有7個元素 ----即scr_el3,esr_el3,runtime_sp,elr_el3,pmcr_el0,is_in_el3

#define DEFINE_REG_STRUCT(name, num_regs) \typedef struct name { \uint64_t ctx_regs[num_regs]; \} __aligned(16) name##_tDEFINE_REG_STRUCT(gp_regs, CTX_EL3STATE_ALL); #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) #define CTX_SCR_EL3 U(0x0) #define CTX_ESR_EL3 U(0x8) #define CTX_RUNTIME_SP U(0x10) #define CTX_SPSR_EL3 U(0x18) #define CTX_ELR_EL3 U(0x20) #define CTX_PMCR_EL0 U(0x28) #define CTX_IS_IN_EL3 U(0x30) #define CTX_EL3STATE_END U(0x40) /* Align to the next 16 byte boundary */

el1_sysregs_t結構體

el1_sysregs_t結構體原型如下，其實就說一個數組uint64_t ctx_regs[num_regs];

#define DEFINE_REG_STRUCT(name, num_regs) \typedef struct name { \uint64_t ctx_regs[num_regs]; \} __aligned(16) name##_tDEFINE_REG_STRUCT(gp_regs, CTX_EL1_SYSREGS_ALL); #define CTX_EL1_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) #define CTX_SPSR_EL1 U(0x0) #define CTX_ELR_EL1 U(0x8) #define CTX_SCTLR_EL1 U(0x10) #define CTX_TCR_EL1 U(0x18) #define CTX_CPACR_EL1 U(0x20) #define CTX_CSSELR_EL1 U(0x28) #define CTX_SP_EL1 U(0x30) #define CTX_ESR_EL1 U(0x38) #define CTX_TTBR0_EL1 U(0x40) #define CTX_TTBR1_EL1 U(0x48) #define CTX_MAIR_EL1 U(0x50) #define CTX_AMAIR_EL1 U(0x58) #define CTX_ACTLR_EL1 U(0x60) #define CTX_TPIDR_EL1 U(0x68) #define CTX_TPIDR_EL0 U(0x70) #define CTX_TPIDRRO_EL0 U(0x78) #define CTX_PAR_EL1 U(0x80) #define CTX_FAR_EL1 U(0x88) #define CTX_AFSR0_EL1 U(0x90) #define CTX_AFSR1_EL1 U(0x98) #define CTX_CONTEXTIDR_EL1 U(0xa0) #define CTX_VBAR_EL1 U(0xa8)

總結

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