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目錄

• • • • 1、gic的版本
      • 2、GICv3/gicv4的模型圖
      • 3、gic中斷號(hào)的劃分
      • 4、GIC連接方式
      • 5、gic的狀態(tài)
      • 6、gic框架
      • 7、gic Configuring

1、gic的版本

GIC是一個(gè)為Cortex-A和Arm Cortex-R設(shè)計(jì)的標(biāo)準(zhǔn)的中斷控制器

2、GICv3/gicv4的模型圖

3、gic中斷號(hào)的劃分

• Shared Peripheral Interrupt (SPI)

• Private Peripheral Interrupt (PPI)

• Software Generated Interrupt (SGI)

• Locality-specific Peripheral Interrupt (LPI)
  
  （使用示例）
  

4、GIC連接方式

5、gic的狀態(tài)

中斷的生命周期:
對(duì)于電平觸發(fā)的中斷(level-sensitive interrupts)，一個(gè)上升沿輸入，將中斷變成pending，中斷信號(hào)線保持高電平直到PE斷言該中斷信號(hào).
對(duì)于邊沿觸發(fā)的中斷(edge-sensitive interrupts)，一個(gè)上升沿輸入，將中斷變成pending，中斷信號(hào)線不會(huì)保持高電平.

6、gic框架

? Distributor interface
? Redistributor interface
? CPU interface

Distributor (GICD_*) for SPIs
? Interrupt prioritization and distribution of SPIs
? Enable and disable SPIs
? Set the priority level of each SPI
? Route information for each SPI
? Set each SPI to be level-sensitive or edge-triggered
? Generate message-signaled SPIs
? Control the active and pending state of SPIs
? Determine the programmer’s model that is used in each Security state: affinity routing or legacy

Redistributors (GICR_*)
? Enable and disable SGIs and PPIs
? Set the priority level of SGIs and PPIs
? Set each PPI to be level-sensitive or edge-triggered
? Assign each SGI and PPI to an interrupt group
? Control the state of SGIs and PPIs
? Control the base address for the data structures in memory that support the associated interrupt properties and pending state for LPIs
? Provide power management support for the connected PE

CPU interfaces (ICC_*_ELn)
? Provide general control and configuration to enable interrupt handling
? Acknowledge an interrupt
? Perform a priority drop and deactivation of interrupts
? Set an interrupt priority mask for the PE
? Define the preemption policy for the PE
? Determine the highest priority pending interrupt for the PE

In Arm CoreLink GICv3, the CPU Interface registers are accessed as System registers: ICC_*_ELn.

7、gic Configuring

全局配置
GICD_CTLR.ARE: Enable Affinity routing (ARE bits), 1-使用gicv3 mode，0-使用legacy mode(gicv2 mode). 默認(rèn)為1
GICD_CTLR.EnableGrp1S
GICD_CTLR.EnableGrp1NS
GICD_CTLR.EnableGrp0

注意在GIC-600 does not support legacy operation

(Redistributor)Settings for each PE
Redistributor中包含了一個(gè)GICR_WAKER寄存器，用于記錄connected PE的狀態(tài)是onLine還是offline. 如果讓PE變成online，軟件則必需這樣做：
? Clear GICR_WAKER.ProcessorSleep to 0.
? Poll GICR_WAKER.ChildrenAsleep until it reads 0

如果PE is offline (GICR_WAKER.ProcessorSleep==1)時(shí)，來了一個(gè)中斷target到該P(yáng)E上，將產(chǎn)一個(gè)wake request信號(hào)，這個(gè)信號(hào)連接PE的power controller，該controller將會(huì)打開PE。然后PE clear the ProcessorSleep bit

CPU interfaces (ICC_*_ELn)

SRE bit— enable cpu interface
注：有些處理器可能不支持legacy operation，SRE比特位也是固定為1，那么軟件就不需要處理該比特了

Set Priority Mask and Binary Point registers
ICC_PMR_EL1、ICC_BPRn_EL1

Set EOI mode （EOI:End of interrupt）
ICC_CTLR_EL1 and ICC_CTLR_EL3

Enable signaling of each interrupt group
ICC_IGRPEN1_EL1 (banked by Security state)
ICC_IGRPEN0_EL1

PE configuration

• Routing controls - SCR_EL3 、 HCR_EL2
• Interrupt masks - PSTATE
• Vector table - VBAR_ELn
  
  
  

interrupt sources configuration

• SPIs are configured through the Distributor, using the GICD_* registers.
• PPIs and SGIs are configured through the individual Redistributors, using the GICR_* registers

對(duì)于每一個(gè)中斷，軟件必需配置的：

• Priority: GICD_IPRIORITYn, GICR_IPRIORITYn
• Group: GICD_IGROUPn, GICD_IGRPMODn, GICR_IGROUPn, GICR_IGRPMODn
• Edge-triggered or level-sensitive: GICD_ICFGRn, GICR_ICFGRn
• Enable: GICD_ISENABLERn, GICD_ICENABLER, GICR_ISENABLERn, GICR_ICENABLERn

Setting the target PE for SPIs

• GICD_IROUTERn.Interrupt_Routing_Mode == 0 rounting到制定的PE
• GICD_IROUTERn.Interrupt_Routing_Mode == 1 Distributor硬件會(huì)自動(dòng)選擇一個(gè)PE，可以是0-n
  A PE can opt out of receiving 1-of-N interrupts. This is controlled by the DPG1S, DPG1NS and DPG0 bits in GICR_CTLR.

Routing a pending interrupt to a PE

• Check that the group associated with the interrupt is enabled
• Check that the interrupt is enabled
• Check the routing controls to decide which PEs can receive the interrupt.
  routing is controlled by GICD_IROUTERn，An SPI can target one specific PE, or any one of the connected PEs
• Check the interrupt priority and priority mask to decide which PEs are suitable to handle the interrupt
  Each PE has a Priority Mask register, ICC_PMR_EL1, in its CPU interface
• Check the running priority to decide which PEs are available to handle the interrup
  Only an interrupt with a higher priority than the running priority can preempt the current interrupt

軟件讀取中斷號(hào)

中斷優(yōu)先級(jí)

中斷結(jié)束End of interrupt

• Priority drop - 將中斷優(yōu)先級(jí)降到中斷產(chǎn)生之前的值
• Deactivation - 將中斷從active變成inactive

在gicv3中，drop和deactivation通常是一起打開的。

ICC_CTLR_ELn.EOImode = 1: 通過寫ICC_EOIR0_EL1、ICC_EOIR1_EL1讓drop and deactivation同時(shí)生效
ICC_CTLR_ELn.EOImode = 0: 通過寫ICC_EOIR0_EL1、ICC_EOIR1_EL1讓drop生效，寫ICC_DIR_EL1讓deactivation生效，這在虛擬化中會(huì)用到.

大多數(shù)的軟件系統(tǒng)中 EOIMode0，而下hypervisor的系統(tǒng)中 EOIMode1

中斷號(hào)的狀態(tài)

產(chǎn)生SGI中斷

PE在secure執(zhí)行時(shí)，可以產(chǎn)生secure和non-secure的SGI;
PE在non-secure執(zhí)行時(shí)，也是可以產(chǎn)生secure的SGI，但是取決于GICR_NSACR寄存器的配置，該寄存器只能在secure中讀寫

比較GICv3和GICv2
在gicv2中，SGI INTIDs對(duì)于originating PE和the target PE是banked
在gicv3中，SGI僅僅對(duì)target PE是banked

在gicv2中同時(shí)收到兩個(gè)SGI=5中斷，兩個(gè)中斷都會(huì)被PE處理。
而在gicv3上，由于originating不是banked，所有前一個(gè)SGI=5中斷將會(huì)丟失。PE只能收到一個(gè)

Legacy operation

? When ARE0, affinity routing is disabled (legacy operation)
? When ARE1, affinity routing is enabled (GICv3 operation)

總結(jié)

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