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Following is an example of a way to perform glitch-free clock gating. The clock is stalled in the high state one clock cycle after gate is asserted high. It is safe as long as the delay through the register is less than a half clock cycle.

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典型的clock gating cell， 可以避免ENL中g(shù)lith的產(chǎn)生。
當(dāng)ck為低電平時(shí),EN可以通過latch,latch 的輸出端信號和EN一致,此時(shí)由于ck為低,ENL=0
當(dāng)ck由低變高時(shí),latch鎖死,latch 的輸出為EN最后的值,c k為高,與門的輸出為EN.當(dāng)然此時(shí)EN一定為高.
所以形成脈沖.

?Low pass latch + AND can gate the rising edge triggered FF. This will make the enable pin has 1T delay. When use Low pass latch + AND, if you pass STA, there will be no glitch. OR gate can also gate the rising edge triggered FF, if you pass STA, there will be also no glitch.
ps: when use write your own gate module, you'd bettern instance the cell library cell directly, this will disable synthesis tool do optimization on your gate logic. and there may have clock gating cells in your cell library now, may named as ICG cell.

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轉(zhuǎn)載于:https://www.cnblogs.com/zhangzhi/archive/2010/10/11/1848275.html

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