S5PV210裸机之SDRAM
1：SDRAM基礎(chǔ)：
通過s3c2440的內(nèi)存原理以及時(shí)序來理解s5pv210 SDRAM原理、時(shí)序。
首先看一下核心板內(nèi)存如何連接的
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?可以看一下兩個(gè)內(nèi)存芯片接的地址總線均為Xm1_ADDR[13:0]，數(shù)據(jù)總線Xm1_DATA[15:0]、Xm1_DATA[31:16]，兩個(gè)內(nèi)存芯片是并聯(lián)的，當(dāng)?shù)刂房偩€Xm1_ADDR[13:0]尋址時(shí)，
可以同時(shí)在兩個(gè)內(nèi)存芯片上各獲取16位數(shù)據(jù)來組成一個(gè)32位數(shù)據(jù)，并由32位數(shù)據(jù)總線輸出。
在看下面這幅圖：下圖為每個(gè)內(nèi)存芯片內(nèi)部框圖：Block Diagram (128Mb x 8)，從圖中可以看出：有8bank：bank0—bank1，BA0-BA2用來選擇bank的，正好可選8個(gè)。
每個(gè)bank的row尋址為14位，列尋址的位10位(行列尋址是共用14位地址總線的，通過不同的時(shí)序來加以區(qū)分，下面會(huì)詳細(xì)介紹時(shí)序)，所以每個(gè)bank的大小為2的24次方bit，為16MB，
一共8個(gè)bank，總共128MB。從核心板圖上可以看出整個(gè)SDRAM，由4對16位內(nèi)存芯片組成，每個(gè)內(nèi)存芯片128MB，其中有兩個(gè)內(nèi)存芯片并聯(lián)成32位內(nèi)存，共256MB內(nèi)存連接在DMC0，
另兩個(gè)內(nèi)存芯片也并聯(lián)成32位內(nèi)存，共256MB連接在DMC1。
?2：內(nèi)存芯片各引腳說明
除去上面介紹的Xm1_ADDR[13:0]做行列地址總線、Xm1_DATA[31:0]作為地址總線以外還有以下接線：
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Xm1_BA[2:0]：bank address，bank選擇引腳；
Xm1_SCLK：內(nèi)存時(shí)鐘；
Xm1_SCLKn：負(fù)時(shí)鐘
Xm1_RASn：行地址選擇；
Xm1_CASn：列地址選擇；
CS：片選；
CKE：命令有效時(shí)鐘；
WE：寫信號(hào)；
DQS：數(shù)據(jù)選通信號(hào)；
DQSn：數(shù)據(jù)選通負(fù)信號(hào)；
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DDR SDRAM時(shí)序詳解：
待補(bǔ)充
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3：代碼詳解
1.2.1.3
DDR2
Initialization sequence for DDR2 memory type:
1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.
2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to ‘1’ to turn on the PHY DLL.
3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value according to clock frequency and memory tAC parameters.
4. Set the PhyControl0.ctrl_start bit-field to ‘1’.
5. Set the ConControl. At this moment, an auto refresh counter should be off.
6. Set the MemControl. At this moment, all power down modes should be off.
7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register.
8. Set the PrechConfig and PwrdnConfig registers.
9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters.
10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.
11. Wait for the PhyStatus0.ctrl_locked bit-fields to change to ‘1’. Check whether PHY DLL is locked.
12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force bit-field to correct value according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.
13. Confirm whether stable clock is issued minimum 200us after power on
14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level.
15. Wait for minimum 400ns.
16. Issue a PALL command using the DirectCmd register.
17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters.
18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters.
19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs.
20. Issue a MRS command using the DirectCmd register to reset the memory DLL.
21. Issue a PALL command using the DirectCmd register.
22. Issue two Auto Refresh commands using the DirectCmd register.
23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL.
24. Wait for minimum 200 clock cycles.
25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS command to exit OCD Calibration Mode and to program the operating parameters.
26. If there are two external memory chips, perform steps 14~25 for chip1 memory device.
27. Set the ConControl to turn on an auto refresh counter. 28. If power down modes is required, set the MemControl registers.
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.global sdram_asm_initsdram_asm_init: ldr r0, =0xf1e00000ldr r1, =0x0str r1, [r0, #0x0]/* DMC0 Drive Strength (Setting 2X) */ldr r0, =ELFIN_GPIO_BASEldr r1, =0x0000AAAAstr r1, [r0, #MP1_0DRV_SR_OFFSET] // 寄存器中對應(yīng)0b10，就是2Xldr r1, =0x0000AAAAstr r1, [r0, #MP1_1DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP1_2DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP1_3DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP1_4DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP1_5DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP1_6DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP1_7DRV_SR_OFFSET]ldr r1, =0x00002AAAstr r1, [r0, #MP1_8DRV_SR_OFFSET]/* DMC1 Drive Strength (Setting 2X) */ldr r0, =ELFIN_GPIO_BASEldr r1, =0x0000AAAAstr r1, [r0, #MP2_0DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_1DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_2DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_3DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_4DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_5DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_6DRV_SR_OFFSET]ldr r1, =0x0000AAAAstr r1, [r0, #MP2_7DRV_SR_OFFSET]ldr r1, =0x00002AAAstr r1, [r0, #MP2_8DRV_SR_OFFSET]首先在初始化DDR之前，引入一個(gè)關(guān)于DRAM Drive Strength的概念----DRAM Drive Strength（也被稱為：driving strength），表示“DRAM驅(qū)動(dòng)強(qiáng)度”。這個(gè)參數(shù)用來控制內(nèi)存數(shù)據(jù)總線的信號(hào)強(qiáng)度，數(shù)值越高代表信號(hào)強(qiáng)度越高，增加信號(hào)強(qiáng)度可以提高超頻的穩(wěn)定性。但是并非信號(hào)強(qiáng)度高就一定好。
所以，這里我們需要配置這個(gè)Drive Striegth，DDR2內(nèi)存的所有線都需要配置，這里我們從地址線開始看，所有的引腳驅(qū)動(dòng)強(qiáng)度都要設(shè)置：
設(shè)置方式：從Xm1ADDR[0:7]對應(yīng)的是PM1_0寄存器，然后查找PM1_0寄存器的地址
?可以看到MP1_0DRV的地址是0xE02003CC，R/W，作用用來設(shè)置驅(qū)動(dòng)強(qiáng)度的寄存器，起始值為0xAAAA，可以看出通過設(shè)置這個(gè)寄存器，我們把Xm1ADDR[0:7]8根地址總線的驅(qū)動(dòng)強(qiáng)度都設(shè)置為2x
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同樣?Xm1ADDR[8:15]對應(yīng)的是PM1_1寄存器，然后查找PM1_1寄存器的地址，地址為0xE02003EC，值設(shè)置為0xAAAA，即對應(yīng)地址總線驅(qū)動(dòng)強(qiáng)度為2x
剩余的按照上面一次類推，注意最后一個(gè)MP1_8的設(shè)置，值需要設(shè)置到MP1_8[4]即可，完成DMC0的驅(qū)動(dòng)強(qiáng)度設(shè)置。
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1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.（為了給控制器和內(nèi)存設(shè)備提供穩(wěn)定的電源，控制器必須把CKE保持為邏輯低電平，然后在應(yīng)用穩(wěn)定的時(shí)鐘，注意：XDDR2SEL應(yīng)該是邏輯高電平才能保持CKE為低。）
一般XDDR2SEL在電路設(shè)計(jì)的時(shí)候直接接到了Vcc，為高電平，所以這個(gè)不用設(shè)置看下圖，如果XDDR2SEL，接在某GPIO上的話需要設(shè)置GPIO輸出高電平才可以；
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2：Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to ‘1’ to turn on the PHY DLL.
根據(jù)時(shí)鐘的頻率，設(shè)置PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc 字段為正確的值。
設(shè)置PhyControl0.ctrl_dll_on字段為1開啟PHY DLL。
/* DMC0 initialization at single Type*/ldr r0, =APB_DMC_0_BASEldr r1, =0x00101000 @PhyControl0 DLL parameter setting, manual 0x00101000str r1, [r0, #DMC_PHYCONTROL0]ldr r1, =0x00000086 @PhyControl1 DLL parameter setting, LPDDR/LPDDR2 Casestr r1, [r0, #DMC_PHYCONTROL1]ldr r1, =0x00101002 @PhyControl0 DLL onstr r1, [r0, #DMC_PHYCONTROL0]ldr r1, =0x00101003 @PhyControl0 DLL startstr r1, [r0, #DMC_PHYCONTROL0]?
根據(jù)時(shí)鐘的頻率，設(shè)置PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc 字段為正確的值。
3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value according to clock frequency and memory tAC parameters.?
DQS清除：設(shè)置the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc位字段，根據(jù)時(shí)鐘頻率和內(nèi)存TAC參數(shù)。
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ctrl_shiftc是粗條，通過控制器的DLL調(diào)整DQS的相移。（0x6 when DDR2 @200MHz）
ctrl_offsetc是精調(diào)，在ctrl_shiftc的基礎(chǔ)上通過控制器的DLL調(diào)整DQS的相移。
ctrl_ref 是DLL同步完成之后需要的一個(gè)延時(shí)。默認(rèn)是4這設(shè)置成8
按照第2步的要求，打開PLL，將PhyControl0.ctrl_dll_on配置為1；
4. Set the PhyControl0.ctrl_start bit-field to ‘1’.
PhyControl0.ctrl_start位的值為'1'
一下幾步是執(zhí)行11、12步檢查DLL
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11. 等待PhyStatus0.ctrl_locked位變?yōu)?#39;1'。檢查是否PHY DLL是否已鎖
find_lock_val:ldr r1, [r0, #DMC_PHYSTATUS] @Load Phystatus register valueand r2, r1, #0x7cmp r2, #0x7 @Loop until DLL is lockedbne find_lock_val12. PHY DLL補(bǔ)償在內(nèi)存操作時(shí)由PVT(Process, Voltage and Temperature，處理器、電壓和溫度)變化引起的延遲量。但是，PHY DLL不能因某些可靠的內(nèi)存操作而切斷，除非是工作在低頻率下。如果關(guān)閉PHY DLL，依照PhyStatus0.ctrl_lock_value[9:2]位的值正確配置PhyControl0.ctrl_force位的值來彌補(bǔ)延遲量(fix delay amount)。清除PhyControl0.ctrl_dll_on位的值來關(guān)閉PHY DLL。
and r1, #0x3fc0 //取出PhyStatus0.ctrl_lock_value[9:2]mov r2, r1, LSL #18 //把r1左移18位放入r2orr r2, r2, #0x100000 //把r2的21位置1orr r2 ,r2, #0x1000 //r2的13位置1orr r1, r2, #0x3 @Force Value locking //r2 0、1bit為置1放入r1str r1, [r0, #DMC_PHYCONTROL0] //r1寫入PhyControl01、DQS是DLL根據(jù)clk產(chǎn)生的信號(hào)，這個(gè)信號(hào)也被稱之為數(shù)據(jù)眼，DQS的主要作用就是告訴控制器何時(shí)讀/寫數(shù)據(jù)。確保數(shù)據(jù)的穩(wěn)定接收和發(fā)送。
小節(jié)：
??? 到了這里，所以關(guān)于DLL的部分就配置完了，主要用到的寄存器只有3個(gè)：PhyControl0，PhyControl1，和PhyStatus0。
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12步之后再才開始之前的第5步：
5. Set the ConControl. At this moment, an auto refresh counter should be off.
?設(shè)置ConControl，此時(shí)應(yīng)關(guān)閉自刷新計(jì)數(shù)器。
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ldr r1, =0x0FFF2010 @ConControl auto refresh offstr r1, [r0, #DMC_CONCONTROL]其中aref_en為0時(shí)就表示關(guān)閉自刷新計(jì)數(shù)器。
rd_fetch的設(shè)置是針對FIFO的讀取時(shí)間的，設(shè)置成2更保險(xiǎn)一點(diǎn)～～（默認(rèn)值是1）
注意：這個(gè)寄存器中有一些有用的值需要注意一下
這兩個(gè)bit位表示dmc0、dmc1、是否接內(nèi)存芯片，根據(jù)實(shí)際情況選擇。
6. Set the MemControl. At this moment, all power down modes should be off.
配置MemControl比較重要的就是以下這幾位，突發(fā)長度，chip個(gè)數(shù)，總線寬度，內(nèi)存類型。
ldr r1, =DMC0_MEMCONTROL //0x00212400 @MemControl BL=4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down offstr r1, [r0, #DMC_MEMCONTROL]?這里注意一些有用信息：BL為4字節(jié)，1 chip、32位 DDR2內(nèi)存。
7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register.
?如果有兩個(gè)外部內(nèi)存芯片，設(shè)置?MemConfig1 register.
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ldr r1, =DMC0_MEMCONFIG_0 // //#define DMC0_MEMCONFIG_0 0x20F01323 @MemConfig0 256MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixedstr r1, [r0, #DMC_MEMCONFIG0]這里的每一個(gè)bit都比較重要，一個(gè)個(gè)解釋一下:
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芯片內(nèi)存的排列方式：交互的；
2、chip_mask 確定一個(gè)chip的映射范圍大小。1表示屏蔽，0表示不屏蔽。
如chip_mask? = F0表示屏蔽高4位，那么映射大小就是：
0X0~0X0FFF_FFFF,也就是256M
如chip_mask? = E0表示屏蔽高3位，那么映射大小就是：
0X0~0X1FFF_FFFF,也就是512M，我們這里設(shè)置的是F0，內(nèi)存為256MB
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1、chip_base DRR的映射地址，默認(rèn)0x2000_0000
// #define DMC0_MEMCONFIG_1 0x30F00312 ldr r1, =DMC0_MEMCONFIG_1 @MemConfig1str r1, [r0, #DMC_MEMCONFIG1]由于沒有用到DMC0_MEMCONFIG_1 ，直接設(shè)置為默認(rèn)值即可。
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step8. Set the PrechConfig? and PwrdnConfig registers.
現(xiàn)在可以開始配置PrechConfig預(yù)充電寄存器和 Pwrdown寄存器，但是damo程序中把 PwrdnConfig registers.的
配置放到了最后一步，所以這里先只講述PrechConfig的配置。
ldr r1, =0xFF000000 @PrechConfig
str r1, [r0, #DMC_PRECHCONFIG]
這個(gè)寄存器用的其實(shí)是默認(rèn)值，具體位的含義可以參考手冊.
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step9. Set the?TimingAref,??TimingRow,??TimingData?and?TimingPower?registers according to memory AC? parameters.?
9.1?TimingAref
#define DMC0_TIMINGA_REF 0x00000618
ldr r1, =DMC0_TIMINGA_REF @TimingAref
str r1, [r0, #DMC_TIMINGAREF]
因?yàn)閐dr是需要不斷的刷新保持?jǐn)?shù)據(jù)的，而這個(gè)刷新間隔不能太長，一般ddr這個(gè)間隔時(shí)間參數(shù)就是7.8us，具體時(shí)間查看ddr手冊。也就是說最長7.8us必須刷新一次。我們不能直接把7.8us告訴arm，必須轉(zhuǎn)換成時(shí)鐘周期數(shù)告訴給arm。及把時(shí)鐘周期數(shù)放到TimingAref.t_refi字段即可。那么周期如何算？首先你得知道此時(shí)提供MCD的時(shí)鐘是多大，比如是133M，那么周期數(shù)就是7.8 us * 133 MHz = 1038 = 0x40E；如果時(shí)鐘是200M那么周期數(shù)就是7.8 us * 200MHz = 1,560= 0x618；
9.2?TimingRow，這個(gè)寄存器主要是配置一些ddr時(shí)序參數(shù)了，這些參數(shù)需要到具體型號(hào)的ddr手冊中去一個(gè)個(gè)的找～～（當(dāng)然同樣，時(shí)間要轉(zhuǎn)換為時(shí)鐘周期數(shù)）
#define DMC0_TIMING_ROW 0x28233287 // TimingRow for @200MHz
ldr r1, =DMC0_TIMING_ROW @TimingRow for @200MHz
str r1, [r0, #DMC_TIMINGROW]
9.3 TimingData?這個(gè)寄存器和上面寄存器一樣，需要到具體型號(hào)的ddr手冊中去一個(gè)個(gè)的找
其中需要注意的是cl，也就是CAS，
ddr手冊中明確說明CAS可以配置為3，4，5，6這幾個(gè)時(shí)鐘周期。值得注意的是，目前我們配置的ddr控制器的CAS，之后還需配置ddr芯片本身的CAS。
所以，我們必須確保這兩個(gè)CAS一致！
還有就是對于DDR2而言，所以wl這參數(shù)不用配置。但是對于低功耗的ddr就必須配置了。
#define DMC0_TIMING_DATA 0x23240304 // TimingData CL=3
ldr r1, =DMC0_TIMING_DATA @TimingData CL=3
str r1, [r0, #DMC_TIMINGDATA]
9.4?TimingPower 也是一樣
#define??? DMC0_TIMING_PWR??????? 0x09C80232??? // TimingPower?
ldr r1, =DMC0_TIMING_PWR @TimingPower
str r1, [r0, #DMC_TIMINGPOWER]
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step10 If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.
現(xiàn)在不用Qos，跳過了～～。。。
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step11 and step12? 被移到了第5步之前了～～
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step13.? Confirm whether stable clock is? issued minimum 200us after power on
由于step11 and step12被提到前面了，所以現(xiàn)在可以不等了～～
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step14～26 這些都是配置ddr芯片（而不是ddr控制器了），都是通過XXX寄存器向ddr芯片發(fā)送命令。
step14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level.
ldr r1, =0x07000000 @DirectCmd chip0 Deselect
str r1, [r0, #DMC_DIRECTCMD]
發(fā)送nop指令將CKE置高
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step15.? Wait for minimum 400ns.
因?yàn)榇饲癈KE一直為高，所以這里無需再等。
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step16. Issue a PALL command using the DirectCmd register.
ldr r1, =0x01000000 @DirectCmd chip0 PALL
str r1, [r0, #DMC_DIRECTCMD]
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step17. Issue an? EMRS2 command using the DirectCmd register to program the operating p
該寄存器作用不大，全部置0
ldr r1, =0x00020000 @DirectCmd chip0 EMRS2
str r1, [r0, #DMC_DIRECTCMD]
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18. Issue an? EMRS3 command using the DirectCmd register to program the operating p
ldr r1, =0x00030000 @DirectCmd chip0 EMRS3
str r1, [r0, #DMC_DIRECTCMD]
以上四個(gè)步驟對應(yīng)下圖：
//----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
19. Issue an? EMRS? command using the DirectCmd register to enable the memory DLLs
這說的EMRS 就是EMRS1.
這里感覺主要就是A10設(shè)置為1，禁止了差分的DQS，而使用單端。
ldr r1, =0x00010400 @DirectCmd chip0 EMRS1 (MEM DLL on, DQS# disable)
str r1, [r0, #DMC_DIRECTCMD]
//----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
20. Issue a MRS command using the DirectCmd register to reset the memory DLL.
這一步配置MRS寄存器就很重要了～～
A8為1，是因?yàn)樵摬襟E說明中明確指明要——reset the memory DLL.
ldr r1, =0x00000542 @DirectCmd chip0 MRS (MEM DLL reset) CL=4, BL=4
str r1, [r0, #DMC_DIRECTCMD]
//----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
21. Issue a PALL command using the DirectCmd register.
再次發(fā)送一個(gè)PALL指令，和16步一樣
ldr r1, =0x01000000 @DirectCmd chip0 PALL
str r1, [r0, #DMC_DIRECTCMD]
//----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
22. Issue two Auto Refresh commands using the? DirectCmd register.
連續(xù)發(fā)送兩個(gè) Auto Refresh指令
ldr r1, =0x05000000 @DirectCmd chip0 REFA
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x05000000 @DirectCmd chip0 REFA
str r1, [r0, #DMC_DIRECTCMD]
//----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
23. Issue a MRS command using the DirectCmd register to program the operating para
the memory DLL.
該步和第20步相同，也是寫MRS，唯一的不同是A8這個(gè)為不同此時(shí)置位1，也就是不再復(fù)位DLL。
ldr r1, =0x00000442 @DirectCmd chip0 MRS (MEM DLL unreset)
str r1, [r0, #DMC_DIRECTCMD]
//----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
24.? Wait for minimum 200 clock cycles.
damo程序中并未等待～～
//----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
25. Issue an? EMRS? command using the DirectCmd register to program the? operating pa
? calibration is not used, issue an EMRS? command to set OCD Calibration Default. Aft
? command to exit OCD Calibration Mode? and to program the operating parameters.
通過寫兩次EMRS1配置OCD校準(zhǔn)，可以看到第一次將OCD_Corr寫成111，之后又寫成000
ldr r1, =0x00010780 @DirectCmd chip0 EMRS1 (OCD default)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00010400 @DirectCmd chip0 EMRS1 (OCD exit)
str r1, [r0, #DMC_DIRECTCMD]
//----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
26. If there are two external memory chips, perform steps 14~25 for chip1 memory device.
如果DMC控制的是兩個(gè)chip那么還需要配置一次chip1，就是把14~25重復(fù)一遍，只不過cmd_chip這個(gè)位要置1.
也就是說，到了這一步，關(guān)于ddr芯片的配置全部結(jié)束了。
ldr r1, =0x07100000 @DirectCmd chip1 Deselect
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x01100000 @DirectCmd chip1 PALL
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00120000 @DirectCmd chip1 EMRS2
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00130000 @DirectCmd chip1 EMRS3
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00110400 @DirectCmd chip1 EMRS1 (MEM DLL on, DQS# disable)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00100542 @DirectCmd chip1 MRS (MEM DLL reset) CL=4, BL=4
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x01100000 @DirectCmd chip1 PALL
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x05100000 @DirectCmd chip1 REFA
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x05100000 @DirectCmd chip1 REFA
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00100442 @DirectCmd chip1 MRS (MEM DLL unreset)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00110780 @DirectCmd chip1 EMRS1 (OCD default)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00110400 @DirectCmd chip1 EMRS1 (OCD exit)
str r1, [r0, #DMC_DIRECTCMD]
//----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
27. Set the ConControl to turn on an auto refresh counter.
到了這一步再次回到ddr控制器的配置。
這一步和第5步只有一處不同，就是aref_en,這里開啟了ddr控制器的自刷新功能。
ldr r1, =0x0FF02030 @ConControl auto refresh on
str r1, [r0, #DMC_CONCONTROL]
//----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
28. If power down modes is required, set the MemControl registers.
還記得第8部嗎？ Set the PrechConfig? and PwrdnConfig registers. 當(dāng)時(shí)damo只配置了PrechConfig 而沒有配置PwrdnConfig ，而在這里
damo程序?qū)wrdnConfig 進(jìn)行了配置。但基本就是按默認(rèn)值配置的。
ldr r1, =0xFFFF00FF @PwrdnConfig
str r1, [r0, #DMC_PWRDNCONFIG]
程序再次設(shè)置了MemControl，這和第6步完全相同。這個(gè)步驟的本意是如果需要power down modes那么就去設(shè)置MemControl去使能相應(yīng)的為，但是damo程序不想
power down modes這個(gè)功能，所以即使配置了PrechConfig也只是“做個(gè)樣子”。
MemControl
ldr r1, =0x00202400 @MemControl BL=4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
str r1, [r0, #DMC_MEMCONTROL]
總結(jié)
以上是生活随笔為你收集整理的S5PV210裸机之SDRAM的全部內(nèi)容，希望文章能夠幫你解決所遇到的問題。
