實(shí)驗(yàn)現(xiàn)象：

先燒寫FPGA程序，再燒寫ARM程序，ARM程序燒寫完畢后即開始讀寫RAM測試，測試成功，綠色ARM·LED亮，測試失敗，紅色ARM·LED閃爍。

核心代碼：

int main(void) {/* USER CODE BEGIN 1 *//* USER CODE END 1 *//* MCU Configuration----------------------------------------------------------*//* Reset of all peripherals, Initializes the Flash interface and the Systick. */HAL_Init();/* USER CODE BEGIN Init *//* USER CODE END Init *//* Configure the system clock */SystemClock_Config();/* USER CODE BEGIN SysInit *//* USER CODE END SysInit *//* Initialize all configured peripherals */MX_GPIO_Init();MX_FSMC_Init();/* USER CODE BEGIN 2 */int i;unsigned short int fsmc_read_data;LED_GREEN_ON;/*?ìé?ledáá￡?±íê?2aê??y3￡oìé?ledáá￡?±íê?2aê?꧰ü￡?2aê??áê?*//* USER CODE END 2 *//* Infinite loop *//* USER CODE BEGIN WHILE */while (1){/* USER CODE END WHILE *//* USER CODE BEGIN 3 */for(i = 0;i < 512;i++){fpga_write(i,i); //?òFPGAD′è?êy?Y } for(i = 0;i < 512;i++){fsmc_read_data = fpga_read(i); //′óFPGA?áêy?Yif(fsmc_read_data != i){LED_GREEN_OFF;LED_RED_ON;while(1);} }}/* USER CODE END 3 */} module FSMC_Ctrl(ab,db,wrn,rdn,csn,PLL_100M,RST_n,nadv);//-------------------------fsmc ------------------------------// input [24:16]ab;inout [15:0]db;input wrn;input rdn;input csn;input PLL_100M;input RST_n; input nadv;wire rd;wire wr;wire [15:0]DB_OUT; //-------------------------rd_wr ----------------------------// assign rd = (csn | rdn);assign wr = (csn | wrn);//-------------------------ab ------------------------------// reg [24:0]address;always @ (posedge nadv or negedge RST_n)beginif(!RST_n)beginaddress <= 25'd0;endelse beginaddress <= {ab,db};endend //-------------------------clk ----------------------------// reg wr_clk1,wr_clk2; always @(posedge PLL_100M or negedge RST_n)beginif(!RST_n)beginwr_clk1 <= 1'd1;wr_clk2 <= 1'd1;endelse{wr_clk2,wr_clk1} <= {wr_clk1,wr}; //提取寫時鐘endwire clk = (!wr_clk2 | !rd);//------------------------db_out -------------------------// assign db = !rd ? DB_OUT : 16'hzzzz;//------------------------ma_ram ------------------------// my_ram u1( //ram塊例化 .address(address),.clock(clk),.data(db),.wren(!wr),.rden(!rd),.q(DB_OUT),);//-------------------------endmodule ------------------------------// endmodule

實(shí)驗(yàn)方法及指導(dǎo)書:

鏈接：http://pan.baidu.com/s/1pLmMprd 密碼：zuet

轉(zhuǎn)載于:https://www.cnblogs.com/xiaomagee/p/7648827.html

總結(jié)

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