數(shù)字電路中經(jīng)常會(huì)遇到需要將時(shí)鐘信號(hào)進(jìn)行分頻，一般分為奇數(shù)分頻和偶數(shù)分頻，同時(shí)對(duì)占空比的要求也不一樣，常見的是需要保持占空比仍為50%。本文通過(guò)Verilog代碼實(shí)現(xiàn)簡(jiǎn)單的分頻電路。文末附上所有代碼和仿真波形。

二分頻

二分頻電路簡(jiǎn)單，只需要一個(gè)D觸發(fā)器，將觸發(fā)器的輸出Q反相之后再接回輸入D端即可完成。

三分頻

三分頻電路比較復(fù)雜一點(diǎn)，因?yàn)橐ＷC占空比為50%，所以勢(shì)必分頻后的時(shí)鐘信號(hào)有一個(gè)沿是跟著輸入時(shí)鐘的下降沿變化的，想清楚這一點(diǎn)，下面的波形圖就很容易得到。

可見需要首先產(chǎn)生兩個(gè)特殊的三分頻的電路，其占空比為1/3，將兩個(gè)信號(hào)或之后就得到了占空比為50%的三分頻信號(hào)。

四分頻

偶數(shù)分頻的電路都比較簡(jiǎn)單，只需要控制好計(jì)數(shù)器進(jìn)行翻轉(zhuǎn)即可。

五分頻

五分頻電路類似三分頻，具體見代碼和仿真波形。

代碼

module divider (input clk,input rst_n,output reg div_clk_2,output wire div_clk_3,output reg div_clk_4,output wire div_clk_5 );//div_2 always @ (posedge clk or negedge rst_n) beginif(!rst_n)div_clk_2 <= 1'b0;elsediv_clk_2 <= ~div_clk_2; end//div_4 reg [1:0] cnt_4; always @ (posedge clk or negedge rst_n) beginif(!rst_n) begincnt_4 <= 0;div_clk_4 <= 0;end else if (cnt_4 == 2'd0) begincnt_4 <= cnt_4 +1;div_clk_4 <= ~div_clk_4;end else if (cnt_4 == 2'd2) begincnt_4 <= cnt_4 +1;div_clk_4 <= ~div_clk_4;end else begincnt_4 <= cnt_4 +1;div_clk_4 <= div_clk_4;end end//div_3_pos reg [1:0] cnt_pos_3; reg div_3_pos; always @ (posedge clk or negedge rst_n) beginif(!rst_n) begincnt_pos_3 <= 0;div_3_pos <= 0;end else if (cnt_pos_3 == 2'b00) begincnt_pos_3 <= cnt_pos_3 +1;div_3_pos <= ~div_3_pos;end else if (cnt_pos_3 == 2'b01) begincnt_pos_3 <= cnt_pos_3 +1;div_3_pos <= ~div_3_pos;end else if (cnt_pos_3 == 2'b10) begincnt_pos_3 <= 0;div_3_pos <= div_3_pos;end end //div_neg_3 reg [1:0] cnt_neg_3; reg div_3_neg; always @ (negedge clk or negedge rst_n) beginif(!rst_n) begincnt_neg_3 <= 0;div_3_neg <= 0;end else if (cnt_neg_3 == 2'b00) begincnt_neg_3 <= cnt_neg_3 +1;div_3_neg <= ~div_3_neg;end else if (cnt_neg_3 == 2'b01) begincnt_neg_3 <= cnt_neg_3 +1;div_3_neg <= ~div_3_neg;end else if (cnt_neg_3 == 2'b10) begincnt_neg_3 <= 0;div_3_neg <= div_3_neg;end endassign div_clk_3=div_3_pos || div_3_neg; //div_5_pos reg [3:0] cnt_pos_5; reg div_5_pos; always @ (posedge clk or negedge rst_n) beginif(!rst_n) begincnt_pos_5 <= 0;div_5_pos <= 0;end else if (cnt_pos_5 == 3'd0) begincnt_pos_5 <= cnt_pos_5 +1;div_5_pos <= ~div_5_pos;end else if (cnt_pos_5 == 3'd2) begincnt_pos_5 <= cnt_pos_5 +1;div_5_pos <= ~div_5_pos;end else if (cnt_pos_5 == 3'd4) begincnt_pos_5 <= 0;div_5_pos <= div_5_pos;end else begincnt_pos_5 <= cnt_pos_5 +1;div_5_pos <= div_5_pos;end end //div_5_neg reg [3:0] cnt_neg_5; reg div_5_neg; always @ (negedge clk or negedge rst_n) beginif(!rst_n) begincnt_neg_5 <= 0;div_5_neg <= 0;end else if (cnt_neg_5 == 3'd0) begincnt_neg_5 <= cnt_neg_5 +1;div_5_neg <= ~div_5_neg;end else if (cnt_neg_5 == 3'd2) begincnt_neg_5 <= cnt_neg_5 +1;div_5_neg <= ~div_5_neg;end else if (cnt_neg_5 == 3'd4) begincnt_neg_5 <= 0;div_5_neg <= div_5_neg;end else begincnt_neg_5 <= cnt_neg_5 +1;div_5_neg <= div_5_neg;end endassign div_clk_5=div_5_pos || div_5_neg;endmodule

仿真波形

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