Verilog有限狀態機(8)

HDLBits鏈接

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前言

今天繼續更新狀態機小節的習題。

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題庫

Q2a:FSM

正宗的FSM題，沒啥說的，看圖寫代碼。

Solution：

module top_module (input clk,input reset, // Synchronous active-high resetinput w,output z );parameter A = 3'd0, B = 3'd1, C = 3'd2;parameter D = 3'd3, E = 3'd4, F = 3'd5;reg [2:0] current_state, next_state;always @(*) begincase(current_state)A: next_state = w ? B : A;B: next_state = w ? C : D;C: next_state = w ? E : D;D: next_state = w ? F : A;E: next_state = w ? E : D;F: next_state = w ? C : D;default:next_state = A;endcaseendalways @(posedge clk) beginif(reset) begincurrent_state <= A;endelse begincurrent_state <= next_state;endendassign z = (current_state == E) | (current_state == F);endmodule

Q2b:One-hot FSM equations

狀態使用獨熱編碼，將狀態中的y[1]和y[3]表示出來。

Solution：

module top_module (input [5:0] y,input w,output Y1,output Y3 );assign Y1 = y[0] & w;assign Y3 = (y[1] | y[2] | y[4] | y[5]) & ~w;endmodule

Q2a:FSM

本題是用狀態機實現一個判優器。其中r1、r2、r3分別表示三種設備的request，g1、g2、g3表示資源的分配情況。由下面的狀態圖可見，設備1,2,3的優先級依次遞減。當設備請求到資源時，需等其完成任務才能釋放資源。

Solution：

module top_module (input clk,input resetn, // active-low synchronous resetinput [3:1] r, // requestoutput [3:1] g // grant );parameter A = 2'd0, B = 2'd1;parameter C = 2'd2, D = 2'd3;reg [1:0] current_state, next_state;always @(*) begincase(current_state)A:beginif(r[1] == 1'b1) beginnext_state = B;endelse if(r[2] == 1'b1) beginnext_state = C;endelse if(r[3] == 1'b1) beginnext_state = D;endelse beginnext_state = A;endendB: next_state = r[1] ? B : A;C: next_state = r[2] ? C : A;D: next_state = r[3] ? D : A;default: next_state = A;endcaseendalways @(posedge clk) beginif(~resetn) begincurrent_state <= A;endelse begincurrent_state <= next_state;endendassign g[1] = current_state == B;assign g[2] = current_state == C;assign g[3] = current_state == D;endmodule

Q2b:Another FSM

該題的狀態機共2輸入2輸出；當復位信號撤銷時，在下一個周期內將f輸出為1，需留意f為1持續一個周期；然后狀態機取決于x的值，當x在連續的三個周期中產生值為1、0、1時，下一周期將g輸出為1，在保持g為1時判斷y的輸入，如果y在兩個周期中有任意一個周期為1了，那么g永久保持1；如果兩個周期都沒有1，那么g將永久保持0。

Solution：

module top_module (input clk,input resetn, // active-low synchronous resetinput x,input y,output f,output g ); parameter IDLE = 4'd0, FOUT = 4'd1, S1 = 4'd2;parameter S2 = 4'd3, S3 = 4'd4, S4 = 4'd5;parameter S5 = 4'd6, ALL_ONE = 4'd7, ALL_ZERO = 4'd8;reg [3:0] current_state, next_state;always @(*) begincase(current_state)IDLE: next_state = FOUT;FOUT: next_state = S1;S1: next_state = x ? S2 : S1;S2: next_state = x ? S2 : S3;S3: next_state = x ? S4 : S1;S4: next_state = y ? ALL_ONE : S5;S5: next_state = y ? ALL_ONE : ALL_ZERO;ALL_ONE: next_state = ALL_ONE;ALL_ZERO: next_state = ALL_ZERO;default: next_state = IDLE;endcaseendalways @(posedge clk) beginif(~resetn) begincurrent_state <= IDLE;endelse begincurrent_state <= next_state;endendassign f = current_state == FOUT;assign g = current_state == S4 | current_state == S5 | current_state == ALL_ONE;endmodule

心得：狀態機設計的好壞決定代碼的難易程度，在畫狀態轉移圖時可以多留點時間。

結語

狀態機這部分題目終于更新完了，自己在做這些題目的過程中收獲也非常大，很感謝該網站的作者。如果代碼哪里有誤，請大家指正，評論區也歡迎大家交流不同的解題思路。

總結

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