Verilog有限狀態(tài)機(jī)(1)

HDLBits鏈接

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前言

今天來(lái)到了重要的部分：狀態(tài)機(jī)。對(duì)該部分內(nèi)容，可能不會(huì)一次更新一個(gè)小節(jié)；一方面是題目難度，另一方面是代碼量過(guò)大；所以該節(jié)會(huì)分批更新，大家見諒。

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題庫(kù)

題目描述1：

實(shí)現(xiàn)下圖所示的摩爾狀態(tài)機(jī)，復(fù)位為異步復(fù)位。

Solution1：

module top_module(input clk,input areset, // Asynchronous reset to state Binput in,output out);// parameter A=0, B=1; reg state, next_state;always @(*) begin // This is a combinational always blockcase(state)A:beginif(in == 1'b1)beginnext_state <= A;endelse beginnext_state <= B;endendB:beginif(in == 1'b1)beginnext_state <= B;endelse beginnext_state <= A;endendendcaseendalways @(posedge clk, posedge areset) begin // This is a sequential always blockif(areset)beginstate <= B;endelse beginstate <= next_state;endend// Output logicassign out = (state == B);endmodule

題目描述2：

實(shí)現(xiàn)下圖所示的摩爾狀態(tài)機(jī)，復(fù)位為同步復(fù)位。

Solution2：

module top_module(input clk,input reset, // Asynchronous reset to state Binput in,output out);// parameter A=0, B=1; reg state, next_state;always @(*) begin // This is a combinational always blockcase(state)A:beginif(in == 1'b1)beginnext_state <= A;endelse beginnext_state <= B;endendB:beginif(in == 1'b1)beginnext_state <= B;endelse beginnext_state <= A;endendendcaseendalways @(posedge clk) begin // This is a sequential always blockif(reset)beginstate <= B;endelse beginstate <= next_state;endend// Output logicassign out = (state == B);endmodule

題目描述3：

2個(gè)輸入1個(gè)輸出，異步復(fù)位狀態(tài)機(jī)，如下圖所示。

Solution3：

module top_module(input clk,input areset, // Asynchronous reset to OFFinput j,input k,output out); // parameter OFF=0, ON=1; reg state, next_state;always @(*) begincase(state)OFF:beginif(j == 0)beginnext_state <= OFF;endelse beginnext_state <= ON;endendON:beginif(k == 0)beginnext_state <= ON;endelse beginnext_state <= OFF;endendendcaseendalways @(posedge clk, posedge areset) beginif(areset)beginstate <= OFF;endelse beginstate <= next_state;endend// Output logicassign out = (state == ON);endmodule

題目描述4：

2個(gè)輸入1個(gè)輸出，同步復(fù)位狀態(tài)機(jī)，如下圖所示。

Solution4：

module top_module(input clk,input reset, // Synchronous reset to OFFinput j,input k,output out); // parameter OFF=0, ON=1; reg state, next_state;always @(*) begincase(state)OFF:beginif(j == 0)beginnext_state <= OFF;endelse beginnext_state <= ON;endendON:beginif(k == 0)beginnext_state <= ON;endelse beginnext_state <= OFF;endendendcaseendalways @(posedge clk) beginif(reset)beginstate <= OFF;endelse beginstate <= next_state;endend// Output logicassign out = (state == ON);endmodule

題目描述5：

實(shí)現(xiàn)下面的摩爾狀態(tài)機(jī)，下表是狀態(tài)轉(zhuǎn)移圖，1輸入1輸出4狀態(tài)。

Solution5：

module top_module(input in,input [1:0] state,output [1:0] next_state,output out); //parameter A=0, B=1, C=2, D=3;always @(*)begincase(state)A:beginif(in == 0)beginnext_state <= A;endelse beginnext_state <= B;endendB:beginif(in == 0)beginnext_state <= C;endelse beginnext_state <= B;endendC:beginif(in == 0)beginnext_state <= A;endelse beginnext_state <= D;endendD:beginif(in == 0)beginnext_state <= C;endelse beginnext_state <= B;endendendcaseendassign out = (state == D);endmodule

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小結(jié)

今天先更新這五道題，主要是熟悉三段式狀態(tài)機(jī)的編寫。

若是代碼有誤請(qǐng)大家提醒我，我一定盡快改正。

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