LIBRARY IEEE; --庫、程序包的說明調(diào)用
USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDER4 IS
PORT
(a,b : IN INTEGER RANGE 0 TO 15;c : OUT INTEGER RANGE 0 TO 15
);
END ADDER4;ARCHITECTURE one OF ADDER4 IS
BEGINc <= a+b;
END one；
方法一：用VHDL寫一個波形信號發(fā)生器
ENTITY SIGGEN IS
PORT
(sig1 : OUT INTEGER RANGE 0 TO 15;sig2 : OUT INTEGER RANGE 0 TO 15
);
ARCHITECTURE Sim OF SIGGEN IS
BEGINsig1<=10,5 AFTER 200 ns,8 AFTER 400 ns;sig2&
