1.仿真預(yù)覽

操作步驟，先格式化。設(shè)置如下：

注意，格式化之后，使用容量如下：

假如我在文檔中保存一個(gè)數(shù)據(jù)

里面數(shù)據(jù)為1

此時(shí)容量使用變?yōu)?#xff1a;

根據(jù)這個(gè)信息，我們最后來驗(yàn)證寫入的數(shù)據(jù)量是否正確。

然后使用我新的下載程序，運(yùn)行后，再次打開，可以看到如下：

按原來的程序，下載后， 其容量為

并提示格式化。

然后按我的新程序，得到結(jié)果如下：

數(shù)據(jù)已經(jīng)被寫入了，由于我們寫入的是bit數(shù)據(jù)，不是實(shí)際的聲音或者視頻，所以沒法看到文件形式，這個(gè)需要借助軟件查看，具體操作如下：

使用我提供給你的這個(gè)軟件。

File>打開路徑。定位到你的SD卡物理路徑，然后點(diǎn)擊

，然后點(diǎn)擊。定位到偏移地址位置。

具體看錄像中顯示效果。

然后這個(gè)軟件也顯示了

使用空間大小。

假如我對(duì)SD卡格式化，重復(fù)上面的操作，結(jié)果如下所示：

具體看錄像中顯示效果。

這樣的話，就讀寫成功了。

2.部分核心代碼

`timescale 1ns / 1ps // // Module Name: sd_write // module sd_write( input SD_clk,output reg SD_cs,output reg SD_datain,input SD_dataout,input init,input [31:0] sec, //寫SD的sec地址input write_req, //寫SD卡請(qǐng)求output reg [3:0] mystate,output reg rx_valid, output reg write_o);parameter idle=4'd0; parameter write_cmd=4'd1; parameter wait_8clk=4'd2; parameter start_taken=4'd3; parameter writea=4'd4; parameter write_crc=4'd5; parameter write_wait=4'd6; parameter write_done=4'd7; //定義要寫入的數(shù)據(jù) wire[7:0]DATAIN; assign DATAIN = 8'h3f;//可以隨便定義 wire [3:0] mystate_o;reg [7:0] rx;reg en;reg [5:0] aa; reg [21:0] cnt;reg [7:0] write_data;reg [47:0] CMD24={8'h58,8'h00,8'h00,8'h00,8'h00,8'hff};//block寫命令CMD24的字節(jié)序列 reg [7:0] Sblock_token=8'hfe; //令牌字reg [7:0] CMDX; reg [7:0] CMDY=8'hff; reg [2:0] cnta;always @(posedge SD_clk) beginrx[0]<=SD_dataout;rx[7:1]<=rx[6:0]; end//接收SD卡的應(yīng)答數(shù)據(jù) always @(posedge SD_clk) beginif(!SD_dataout&&!en)begin rx_valid<=1'b0; aa<=1;en<=1'b1;end //等待SD_dataout為低,SD_dataout為低,開始接收數(shù)據(jù)else if(en) begin if(aa<7) beginaa<=aa+1'b1; rx_valid<=1'b0;endelse beginaa<=0;en<=1'b0;rx_valid<=1'b1; //接收完第8bit后,rx_valid信號(hào)開始有效endendelse begin en<=1'b0;aa<=0;rx_valid<=1'b0;end end//SD卡寫程序 always @(negedge SD_clk) if(!init)beginmystate<=idle;CMD24<={8'h58,8'h00,8'h00,8'h00,8'h00,8'hff};write_o<=1'b0;end elsebegincase(mystate)idle: beginSD_cs<=1'b1;SD_datain<=1'b1;cnt<=22'd0; if(write_req) begin //如果有寫請(qǐng)求 mystate<=write_cmd;CMD24<={8'h58,sec[31:24],sec[23:16],sec[15:8],sec[7:0],8'hff};Sblock_token<=8'hfe;write_o<=1'b0;endelse mystate<=idle;endwrite_cmd: begin //發(fā)送CMD24命令 (single Block write) if(CMD24!=48'd0) beginSD_cs<=1'b0;SD_datain<=CMD24[47];CMD24<={CMD24[46:0],1'b0}; //移位輸出,高位在先 endelse begin if(rx_valid) begin //等待應(yīng)答信號(hào) cnta<=7;mystate<=wait_8clk;SD_cs<=1'b1;SD_datain<=1'b1; endendendwait_8clk: begin //寫數(shù)據(jù)之前等待8clockif(cnta>0) begincnta<=cnta-1'b1;SD_cs<=1'b1;SD_datain<=1'b1;endelse beginSD_cs<=1'b1;SD_datain<=1'b1;mystate<=start_taken;cnta<=7;endend start_taken: begin //發(fā)送Start Block Takenif(cnta>0) begincnta<=cnta-1'b1;SD_cs<=1'b0;SD_datain<=Sblock_token[cnta]; //高位在先發(fā)送endelse beginSD_cs<=1'b0;SD_datain<=Sblock_token[0];mystate<=writea;cnta<=7;cnt<=0;endendwritea: begin //寫字節(jié)到SD卡if(cnt<512) begin if(cnta>0) beginSD_cs<=1'b0;SD_datain<=DATAIN[cnta];cnta<=cnta-1'b1;endelse beginSD_cs<=1'b0;SD_datain<=DATAIN[0];cnta<=7;cnt<=cnt+1'b1;endendelse begin if(cnta>0) beginSD_datain<=DATAIN[cnta];cnta<=cnta-1'b1;endelse beginSD_datain<=DATAIN[cnta];cnta<=7;cnt<=0;mystate<=write_crc; endendendwrite_crc: begin //寫crc:0xff,0xffif(cnt<16) beginSD_cs<=1'b0;SD_datain<=1'b1;cnt<=cnt+1'b1;endelse beginif(rx_valid) //等待Data Response Tokenmystate<=write_wait;elsemystate<=write_crc; endendwrite_wait: begin //等待數(shù)據(jù)寫入完成,if(rx==8'hff) beginmystate<=write_done; endelse begin mystate<=write_wait;endendwrite_done:beginif(cnt<22'd15) begin //等待15個(gè)clockSD_cs<=1'b1;SD_datain<=1'b1;cnt<=cnt+1'b1;endelse beginmystate<=idle;write_o<=1'b1; cnt<=0;end end default:mystate<=idle;endcase end endmodule `timescale 1ns / 1psmodule sd_test(input clk, //50Mhz input clock input rst_n,output SD_clk, //25Mhz SD SPI時(shí)鐘 output SD_cs, //SD SPI片選 output SD_datain, //SD SPI數(shù)據(jù)輸入 input SD_dataout, //SD SPI數(shù)據(jù)輸出 output led);reg rst_n2=1'b0; reg[31:0]cnt=32'd0; always @(posedge clk) begin cnt<=cnt+32'd1; if(cnt==32'h00ff_ffff) rst_n2<=1'b1; else rst_n2<=rst_n2; endassign led=~rst_n2;wire SD_datain_i; wire SD_datain_w; wire SD_datain_r; reg SD_datain_o;wire SD_cs_i; wire SD_cs_w; wire SD_cs_r; reg SD_cs_o;//PLL產(chǎn)生25Mhz的SD卡SPI時(shí)鐘 pll pll_inst(.areset (~rst_n2),.inclk0 (clk),.c0 (SD_clk),.locked ());reg [31:0]read_sec; reg read_req;reg [31:0]write_sec; reg write_req;wire [7:0]mydata_o/* synthesis keep */; wire myvalid_o/* synthesis keep */;wire init_o/* synthesis keep */; //SD 初始化完成標(biāo)識(shí) wire write_o; //SD blcok寫完成標(biāo)識(shí) wire read_o; //SD blcok讀完成標(biāo)識(shí)reg [3:0] sd_state;wire [3:0] initial_state; wire [3:0] write_state; wire [3:0] read_state;wire rx_valid;parameter STATUS_INITIAL=4'd0; parameter STATUS_WRITE=4'd1; parameter STATUS_READ=4'd2; parameter STATUS_IDLE=4'd3;assign SD_cs = SD_cs_o; assign SD_datain = SD_datain_o;always @ ( posedge SD_clk or negedge rst_n2 )if( !rst_n2 ) beginsd_state <= STATUS_INITIAL;read_req <= 1'b0;read_sec <= 32'd0;write_req <= 1'b0;write_sec <= 32'd0; endelse case( sd_state )STATUS_INITIAL:if( init_o ) begin sd_state <= STATUS_WRITE; write_sec <= 32'd0; write_req <= 1'b1; endelse begin sd_state <= STATUS_INITIAL; end STATUS_WRITE:if( write_o ) begin sd_state <= STATUS_IDLE; endelse begin write_req<= 1'b0; sd_state <= STATUS_WRITE; endSTATUS_IDLE: sd_state <= STATUS_IDLE;default: sd_state <= STATUS_IDLE;endcase//SD卡初始化程序 sd_initial sd_initial_inst( .rst_n(rst_n2),.SD_clk(SD_clk),.SD_cs(SD_cs_i),.SD_datain(SD_datain_i),.SD_dataout(SD_dataout),.rx(),.init_o(init_o),.state(initial_state));//write sd_write sd_write_inst( .SD_clk(SD_clk),.SD_cs(SD_cs_w),.SD_datain(SD_datain_w),.SD_dataout(SD_dataout),.init(init_o),.sec(32'd16448),.write_req(write_req),.mystate(write_state),.rx_valid(rx_valid),.write_o(write_o) );always @(*) begincase( sd_state )STATUS_INITIAL: begin SD_cs_o<=SD_cs_i;SD_datain_o<=SD_datain_i; endSTATUS_WRITE: begin SD_cs_o<=SD_cs_w;SD_datain_o<=SD_datain_w; enddefault: begin SD_cs_o<=1'b1;SD_datain_o<=1'b1; end endcase endendmodule

A38-11

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